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Adventurer
Adventurer
3,050 Views
Registered: ‎05-27-2013

IPcore of QDR2plus memory controller ucf problem

hi

 

    when i am genarrating the UCF for the ipcore. the ipcore had genarated the UCF. But i made my changes in the pin cofiguration .

I have used the ipcore to cross check my UCF file with Design File. It is showing error in the connection

 

         Verification Report

 

Generated by MIG Version 3.6 on Mon May 27 14:27:26 2013

Reading design libraries of xc6vhx565t-ff1923... successful !

 

/*******************************************************/

/* Controller 0

/*******************************************************/

ERROR: System clock banks can be selected either in the GC bank 25,35,24,34 or in the inner column banks which are in the same H-Row of Capture Clock bank 37.

 

Verification completed.

Number of pin allocation errors = 1.

 

 I have given the system clock to my clock from the banks 35,34

how to clear this error

 

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2 Replies
Scholar austin
Scholar
3,038 Views
Registered: ‎02-27-2008

Re: IPcore of QDR2plus memory controller ucf problem

read the users guide!

Austin Lesea
Principal Engineer
Xilinx San Jose
Adventurer
Adventurer
3,018 Views
Registered: ‎05-27-2013

Re: IPcore of QDR2plus memory controller ucf problem

I have read the used guide. In the user guide i did find about it. Please help in this .Please provide example 

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