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Visitor
Visitor
5,263 Views
Registered: ‎03-07-2013

ISim Fatal Error on X_RAMB18E1

Hi everybody! :)

I'm quite new in using Xilinx software and I have I trouble in an ISim post-PAR simulation of my project on a Virtex-6 XC6VLX760 device. In particular, simulation stops at certain point and displays the message:

 

"ERROR: In process X_RAMB18E1.vhd:prcs_clk

FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

INFO: Simulator is stopped."

 

I guess it's a problem related to block RAM memory, but has anyone of you an idea about what kind of problem is it?

If you need to know, I'm using ISE 14.4 with a Linux-64 OS.

 

Thanks in advance,

Antonio.

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Moderator
Moderator
5,253 Views
Registered: ‎01-16-2013

Hi antda,

 

For any FATAL error please fill webcase with Xilinx Technical Support 

http://www.xilinx.com/support/clearexpress/websupport.htm

 

Thanks,

Syed

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Visitor
Visitor
5,250 Views
Registered: ‎03-07-2013

Hi Syed,

 

I'll do as soon as possible.

 

Thank you,

Antonio

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Moderator
Moderator
5,246 Views
Registered: ‎01-16-2013

Your welcome Antonio.

Do remeber to attach the design files when you create a webcase.

It will reduce the time to resolve your issue.

 

Regards,

Syed

 

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Visitor
Visitor
5,236 Views
Registered: ‎03-07-2013

Dear Syed,

I discvered I can't open a webcase with my student account. And, anyway, I couldn't attach design files for discretion issue.

Have you any suggestion for me?

 

Thanks again...

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Visitor
Visitor
3,254 Views
Registered: ‎04-06-2015

Hi, did you solved this problem?

I have a similar problem, can anyone help me?

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Xilinx Employee
Xilinx Employee
3,250 Views
Registered: ‎07-21-2014

Hi,

 

can you please share design to reproduce this issue?

 

thanks,

Shreyas

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Visitor
Visitor
3,244 Views
Registered: ‎04-06-2015

All components are created with Core Generator

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY XilinxCoreLib;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Memory_top is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
write_en : in STD_LOGIC;
read_en : in STD_LOGIC;
raw_fft : IN STD_LOGIC;--if raw_fft=0, cpu wants to read raw data, else cpu wants to read fft.
read_address : IN std_logic_vector (15 downto 0);
full : out STD_LOGIC;
empty : out STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout_im : out STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0));
end Memory_top;

architecture Behavioral of Memory_top is

--------------------constants---------------------
constant High : std_logic := '1';
constant Low : std_logic := '0';
--------------------components--------------------
COMPONENT CNT
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;

COMPONENT Memory
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;

COMPONENT BRAM_raw
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;

COMPONENT FFT
PORT (
clk : IN STD_LOGIC;
start : IN STD_LOGIC;
xn_re : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
xn_im : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fwd_inv : IN STD_LOGIC;
fwd_inv_we : IN STD_LOGIC;
rfd : OUT STD_LOGIC;
xn_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
busy : OUT STD_LOGIC;
edone : OUT STD_LOGIC;
done : OUT STD_LOGIC;
dv : OUT STD_LOGIC;
xk_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
xk_re : OUT STD_LOGIC_VECTOR(42 DOWNTO 0);
xk_im : OUT STD_LOGIC_VECTOR(42 DOWNTO 0)
);
END COMPONENT;

COMPONENT CNT1024
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;

COMPONENT Bram
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;

COMPONENT CNT64
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
-----------------signals------------------------------
signal data : std_logic_vector (31 downto 0);
signal start : std_logic;
signal aempty_fifo : std_logic;
signal full_fifo : std_logic;
signal rd_en_fifo : std_logic;
signal wr_en_bram_raw : std_logic_vector (0 downto 0);
signal en_bram_raw : std_logic;
signal raw_rd_en : std_logic;
signal fft_rd_en : std_logic;
signal wr_addres_bram_raw_cnt_en : std_logic;
signal wr_address_bram_raw : std_logic_vector (15 downto 0);
signal rd_address_bram_raw : std_logic_vector (15 downto 0);
signal im_data : std_logic_vector (31 downto 0);
signal xn_index: std_logic_vector (9 downto 0);
signal rfd : std_logic;
signal busy : std_logic;
signal edone : std_logic;
signal done : std_logic;
signal dv :std_logic;
signal xk_index: std_logic_vector (9 downto 0);
signal xk_re : std_logic_vector (42 downto 0);
signal xk_im : std_logic_vector (42 downto 0);
signal Dout_im_int : std_logic_vector (31 downto 0);
signal Dout_fft : std_logic_vector (31 downto 0);
signal Dout_raw : std_logic_vector (31 downto 0);
signal din_fft_im : std_logic_vector (31 downto 0);
signal din_fft_re : std_logic_vector (31 downto 0);
signal wr_en_fft : std_logic_vector (0 downto 0);
signal address_fft : std_logic_vector (15 downto 0);
signal upper_address : std_logic_vector (5 downto 0);

begin
address_fft(15 downto 10)<=upper_address;
address_fft(9 downto 0)<=xk_index;
rd_en_fifo<= (not full_fifo) and (not aempty_fifo);
raw_rd_en<=not raw_fft and read_en;
fft_rd_en<= raw_fft and read_en;
en_bram_raw<=wr_en_bram_raw(0);
full<=full_fifo;
im_data<= (others =>'0');
wr_en_fft(0)<=done;
din_fft_im<=xk_im(31 downto 0);
din_fft_re<=xk_re(31 downto 0);

FIFO : Memory
PORT MAP (
clk => clk,
rst => reset,
din => din,
wr_en => write_en,
rd_en => rd_en_fifo,
dout => data,
full => full_fifo,
empty => empty,
prog_empty => aempty_fifo
);

Bram_raw_0 : BRAM_raw
PORT MAP (
clka => clk,
ena => en_bram_raw,
wea => wr_en_bram_raw,
addra => wr_address_bram_raw,
dina => data,
clkb => clk,
enb => raw_rd_en,
addrb => read_address,
doutb => Dout_raw
);

cnt_wr_address_braw : CNT
PORT MAP (
clk => clk,
ce => wr_en_bram_raw(0),
q => wr_address_bram_raw
);

FFT_1024 : FFT
PORT MAP (
clk => clk,
start => en_bram_raw,
xn_re => data,
xn_im => im_data,
fwd_inv => High,
fwd_inv_we => Low,
rfd => rfd,
xn_index => open,
busy => busy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im
);

 

Bram_FFT_re : BRAM_raw
PORT MAP (
clka => clk,
ena => done,
wea => wr_en_fft,
addra => address_fft,
dina => din_fft_re,
clkb => clk,
enb => fft_rd_en,
addrb => read_address,
doutb => Dout_fft
);

Bram_FFT_im : BRAM
PORT MAP (
clka => clk,
ena => done,
wea => wr_en_fft,
addra => address_fft,
dina => din_fft_im,
clkb => clk,
enb => fft_rd_en,
addrb => read_address,
doutb => Dout_im_int
);

upper_address_cnt : CNT64
PORT MAP (
clk => clk,
ce => edone,
q => upper_address
);

reg_0: FDCE
generic map (INIT => '0')
port map (D=>rd_en_fifo, C=>clk, CE=>High, CLR=>reset, Q=>wr_en_bram_raw(0));

reg_1: FDCE
generic map (INIT => '0')
port map (D=>wr_en_bram_raw(0), C=>clk, CE=>High, CLR=>reset, Q=>wr_addres_bram_raw_cnt_en);


mux_process:process(reset,clk)
begin
if (reset='0') then
Dout<=(others =>'0');
Dout_im<=(others =>'0');
elsif (clk'event and clk='1') then
if raw_fft='1' then
Dout_im<=Dout_im_int;
Dout<=Dout_fft;
else
Dout_im<=(others => '0');
Dout<=Dout_raw;
end if;
end if;
end process;

end Behavioral;

 

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Memory_top_tb IS
END Memory_top_tb;

ARCHITECTURE behavior OF Memory_top_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Memory_top
PORT(
clk : IN std_logic;
reset : IN std_logic;
write_en : IN std_logic;
read_en : IN std_logic;
raw_fft : IN std_logic;
read_address : IN std_logic_vector(15 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
Din : IN std_logic_vector(31 downto 0);
Dout_im : out STD_LOGIC_VECTOR (31 downto 0);
Dout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal write_en : std_logic := '0';
signal read_en : std_logic := '0';
signal raw_fft : std_logic := '0';
signal read_address : std_logic_vector(15 downto 0) := (others => '0');
signal Din : std_logic_vector(31 downto 0) := (others => '0');

--Outputs
signal full : std_logic;
signal empty : std_logic;
signal Dout : std_logic_vector(31 downto 0);
signal Dout_im : std_logic_vector(31 downto 0);

-- Clock period definitions
constant clk_period : time := 8 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Memory_top PORT MAP (
clk => clk,
reset => reset,
write_en => write_en,
read_en => read_en,
raw_fft => raw_fft,
read_address => read_address,
full => full,
empty => empty,
Din => Din,
Dout_im => Dout_im,
Dout => Dout
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 104 ns;
reset<='0';
wait for clk_period*10;
write_en<='1';
wait for 3 ns;
Din<=x"AAAAAAAA";
wait for 8 ns;
Din<=x"55555555";
wait for 8 ns;
Din<=x"33333333";
wait for 8 ns;
Din<=x"11111111";
wait for 8 ns;
Din<=x"AAAAAAAA";
wait for 8 ns;
Din<=x"55555555";
wait for 8 ns;
Din<=x"AAAAAAAA";
wait for 8 ns;
Din<=x"55555555";
wait for 8 ns;
Din<=x"AAAAAAAA";
...

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Highlighted
Visitor
Visitor
3,242 Views
Registered: ‎04-06-2015

Thx, in advance :)

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Visitor
Visitor
3,218 Views
Registered: ‎04-06-2015

This is my full design...

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