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Observer
Observer
3,827 Views
Registered: ‎04-18-2012

In TestBench initialised values aren't "used" in ISim

Hi everybody,

 

once again I have a question where I can't find an answer. The thing is that if I initialise an input, or the signal connected to that input, the input is on the orange "undefined" level and not on one or two. Sometimes it seems to work and sometimes not. Here is how I declared the inputs:

 

COMPONENT FFT_Module
      PORT(
           clk_50M : IN std_logic;

            reset : IN std_logic;

            start_TB  : IN std_logic

                );

 

signal reset : std_logic;
 signal clk_50M : std_logic;

signal start_TB :std_logic;

 

begin

 

uut: FFT_Module PORT MAP (
              clk_50M => clk_50M,
               reset => reset,    

               start_TB => start_TB

                          );

 

-- Clock process definitions
clk_process : process
       begin
              clk_50M <= '0';
         wait for 10ns;
              clk_50M <= '1';
         wait for 10ns;
end process;


  start_TB <= '0', '1' after 200ns, '0' after 25us;
   reset <= '1', '0' after 10ns;

 

END;

 

This is how it looks in ISim afterwards:

 

Capture.JPG 

 

 Do I miss something? Is there anything else to define to make the testbench work properly?

 

Thanks in advance!

 

Regards,

 

Lenni 

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5 Replies
Highlighted
Teacher
Teacher
3,813 Views
Registered: ‎08-14-2007

Re: In TestBench initialised values aren't "used" in ISim

Hi Lenni,

6ps vs 10 us is quite some short time.

Have you really run your simulation at all?

 

when you see this window try the following commands:

 

restart

run 100us

 

some message like this should appear:

     Simulator is doing circuit initialization process.

     Finished circuit initialization process.

 

Then you should also be able to see something in the waveform. (Make a full zoom)

Also, since your FFT instance has only inputs yet, maybe you can comment it out, so you just have the testbench generating some signals.

 

If still nothing happens, there seems to be some other problem.

Check the outputs of ISIM for error or warning messages.

 

Have a nice simulation

  eilert

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Observer
Observer
3,812 Views
Registered: ‎04-18-2012

Re: In TestBench initialised values aren't "used" in ISim

Hey Eilert. 

 

jap the timing definitelly is something to rethink about again.  Anyways, I figured out why my testbench didn't work properly (the code above is just an example and not exactly my code. That would be to much). All I did was marking the wrong file in the Hierarchy. Now where I marked my testbench the simulation runs properly. Except of one thing that really bugs me.

 

The signals seem not to get from the TestBench threw the top Modell to the FFT.

 

Let me quickly abload the code of the two files:

 

Test Bench:

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use std.textio.all;
use ieee.numeric_std.all;
-- use UNISIM.VComponents.all;


 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY FFT_TestBench_update1 IS
END FFT_TestBench_update1;
 
ARCHITECTURE behavior OF FFT_TestBench_update1 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FFT_Module
    PORT(
			clk_50M : IN std_logic;
			reset : IN std_logic;
         Adu_Chip_Select : OUT  std_logic;
         Adu_Clock_Pin : OUT  std_logic;
         --Data_From_ADU_HW : OUT  std_logic;
         Green_LED : OUT  std_logic;
         Red_LED : OUT  std_logic;
         Blue_LED : OUT  std_logic;
			Sample_Avail : IN std_logic;
			
			start_TB   : IN std_logic;
			unload_TB :  OUT std_logic;
			Data_in_TB : IN std_logic_vector(11 downto 0);
			fwd_inv_TB : IN STD_LOGIC;
			fwd_inv_we_TB : IN STD_LOGIC;
			scale_sch_TB : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
			scale_sch_we_TB : IN STD_LOGIC;
			
			rfd_test : OUT STD_LOGIC;
			xn_index_test : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
			busy_test : OUT STD_LOGIC;
			done_test : OUT STD_LOGIC;
			xk_index_test : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
			xk_re_test : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
			xk_im_test : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
			
			test 		: out std_logic;
			test2		: out std_logic;
			test3		: out std_logic;
			test4		: out std_logic;
			test_count : out std_logic_vector(9 downto 0);
			test_vector : out std_logic_vector(11 downto 0)
        );
    END COMPONENT;
    
	 

   --Inputs
   signal Adu_Chip_Select : std_logic := '0';
   signal Adu_Clock_Pin : std_logic := '0';
	signal data_in_sig : std_logic_vector(11 downto 0) := "000000000000";

	signal reset : std_logic := '1';
	signal clk_50M : std_logic := '0';
 	--Outputs
   -- signal Data_From_ADU_HW : std_logic := '0';
   signal Green_LED : std_logic := '0';
   signal Red_LED : std_logic := '0';
   signal Blue_LED : std_logic := '0';
	signal sample_avail : std_logic := '0';
	
	signal start : std_logic := '0';
	signal unload_sig : std_logic := '0';
	signal rfd : STD_LOGIC := '0';
	signal fwd_inv : STD_LOGIC := '1';
   signal fwd_inv_we : STD_LOGIC := '1';
   signal scale_sch : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
   signal scale_sch_we : STD_LOGIC := '0';
	 
   signal xn_index: STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000";
   signal busy : STD_LOGIC := '0';
   signal edone : STD_LOGIC := '0';
   signal done : STD_LOGIC := '0';
   signal xk_index :  STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000";
   signal xk_re :  STD_LOGIC_VECTOR(11 DOWNTO 0) := "000000000000";
   signal xk_im : STD_LOGIC_VECTOR(11 DOWNTO 0) := "000000000000";
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
	
	signal test : std_logic := '0';
	signal test2 : std_logic := '0';
	signal test3 : std_logic := '0';
	signal test4 : std_logic := '0';
	signal test_count : std_logic_vector(9 downto 0) := "0000000000";
	signal test_vector: std_logic_vector(11 downto 0) := "000000000000";
	
	
 
BEGIN
 
--	 Instantiate the Unit Under Test (UUT)
   uut: FFT_Module PORT MAP (
			 clk_50M => clk_50M,
			 reset => reset,
			 
          Adu_Chip_Select => Adu_Chip_Select,
          Adu_Clock_Pin => Adu_Clock_Pin,
          --Data_From_ADU_HW => Data_From_ADU_HW,
          Green_LED => Green_LED,
          Red_LED => Red_LED,
          Blue_LED => Blue_LED,
			 Sample_Avail => sample_avail,
			 
			 Data_in_TB => data_in_sig,
			 start_TB => start,
			 unload_TB => unload_sig,
			 xn_index_test => xn_index,
			 busy_test => busy,
			 
			 done_test => done,
			 xk_index_test => xk_index,
			 xk_re_test => xk_re,
			 xk_im_test => xk_im,
			 
			test 		=> test,
			test2		=> test2,
		  	test3		=> test3,
			test4		=> test4,
			
			test_count => test_count,
			test_vector => test_vector,
			
			 fwd_inv_TB			=> fwd_inv,
			 fwd_inv_we_TB		=> fwd_inv_we,
			 scale_sch_TB		=> scale_sch,
			 scale_sch_we_TB	=> scale_sch_we
        );
 Get_Data : process(clk_50M,reset, xn_index)
			type Signed_File is file of std_logic_vector(11 downto 0);
			file myfile : text is "Test_Data.txt";
			variable inline : line;
			variable data_in : integer;
			variable end_of_line : boolean;
			
		begin
		if reset = '1' then
			data_in := 0;
			end_of_line := FALSE;
			
			
		elsif clk_50M'event and clk_50M = '1' then
			 data_in := 0;
		--	 start <= '1';
			 sample_avail <= '1';
			 
			if (not endfile (myfile) and xn_index < "1111111111") then
				readline(myfile, inline);
				read(inline, data_in, end_of_line); 
				data_in_sig <= std_logic_vector(to_signed(data_in,12));	
			end if;
			
				
		end if;

end process Get_Data;
	
	
   -- Clock process definitions
   clk_process : process
   begin
		clk_50M <= '0';
		wait for 10ns;
		clk_50M <= '1';
		wait for 10ns;
   end process;

	
   start <= '0', '1' after 200ns, '0' after 35us;
 --  unload_sig <= '0', '1' after 26us;
	reset <= '1', '0' after 50ns;
	fwd_inv_we <= '1', '0' after 40ns;
	fwd_inv	  <= '1', '0' after 60ns;
	
END;

 

 And here the TopModell:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;									
use IEEE.std_logic_arith.all;									
use ieee.numeric_std.all;										
use IEEE.std_logic_signed.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FFT_Module is
	Port(
	-----------------------------
	--------  generell  ---------
	-----------------------------
	reset : IN std_logic;
	clk_50M    : IN std_logic; -- 50MHz clock	
	-----------------------------
	--------  TestBench  --------
	-----------------------------

	start_TB   : IN std_logic;
	unload_TB  : OUT std_logic;
	Data_in_TB : IN std_logic_vector(11 downto 0);
	fwd_inv_TB : IN STD_LOGIC;
   fwd_inv_we_TB : IN STD_LOGIC;
   scale_sch_TB : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
   scale_sch_we_TB : IN STD_LOGIC;
	 
   rfd_test : OUT STD_LOGIC;
   xn_index_test : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
   busy_test : OUT STD_LOGIC;
   done_test : OUT STD_LOGIC;
   xk_index_test : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
   xk_re_test : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
   xk_im_test : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	
	test 		: out std_logic;
	test2		: out std_logic;
	test3		: out std_logic;
	test4		: out std_logic;
	test_count : out std_logic_vector(9 downto 0);
	test_vector : out std_logic_vector(11 downto 0);
	
	-----------------------------
	----------  ADU  ------------
	-----------------------------
	Adu_Chip_Select : OUT std_logic;  -- from Frequency divider
	Adu_Clock_Pin   : OUT std_logic;  -- from Frequency divider
	Sample_Avail    : IN std_logic;
	-- Data_From_ADU_HW: OUT std_logic;
	
	-----------------------------
	----------  LED  ------------
	-----------------------------
	 Green_LED : OUT std_logic;
	 Red_LED   : OUT std_logic;
	 Blue_LED: OUT std_logic
	 );
end FFT_Module;

architecture Behavioral of FFT_Module is
	--TYPES
	type vector is array (natural range 0 to 1024) of std_logic_vector(11 downto 0);
	
	-- SIGNALS

	signal clk_div : STD_LOGIC;
	
	-----------------------------
	----------  ADU  ------------
	-----------------------------
	-- Input
	signal adu_chip_select_sig, adu_nchip_select_sig : STD_LOGIC;
	signal clk_adu_sig			: STD_LOGIC;
	
	-- Output
	signal audio_sample_signal : STD_LOGIC_VECTOR(11 downto 0); -- to transport Audio sample from ADU-Component to the sample vector
	signal sample_avail_sig		: STD_LOGIC;
	signal adu_clock_pin_sig 	: STD_LOGIC;
	signal data_from_adu_hw_sig: STD_LOGIC;
	-----------------------------
	----------  FFT  ------------
	-----------------------------
	-- Input
	 signal Res : STD_LOGIC;
    signal clk_fft : STD_LOGIC;
    signal start : STD_LOGIC;
    signal unload : STD_LOGIC;
    signal xn_re : STD_LOGIC_VECTOR(11 DOWNTO 0);
    signal xn_im : STD_LOGIC_VECTOR(11 DOWNTO 0);
    signal fwd_inv : STD_LOGIC;
    signal fwd_inv_we : STD_LOGIC;
    signal scale_sch : STD_LOGIC_VECTOR(19 DOWNTO 0);
    signal scale_sch_we : STD_LOGIC;
	 
	-- Outputs
    signal rfd : STD_LOGIC;
    signal xn_index : STD_LOGIC_VECTOR(9 DOWNTO 0);
    signal busy : STD_LOGIC;
    signal edone : STD_LOGIC;
    signal done : STD_LOGIC;
    signal dv : STD_LOGIC;
    signal xk_index :  STD_LOGIC_VECTOR(9 DOWNTO 0);
    signal xk_re :  STD_LOGIC_VECTOR(11 DOWNTO 0);
    signal xk_im : STD_LOGIC_VECTOR(11 DOWNTO 0);
	
	-----------------------------
	------  Test Bench  ---------
	-----------------------------
	signal test3_sig : std_logic; 
	
COMPONENT FFT_Core
  PORT (
	-- Inputs:
    clk : IN STD_LOGIC;
    start : IN STD_LOGIC;
    unload : IN STD_LOGIC;
    xn_re : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    xn_im : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    fwd_inv : IN STD_LOGIC;
    fwd_inv_we : IN STD_LOGIC;
    scale_sch : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
    scale_sch_we : IN STD_LOGIC;
	 
	 
	-- Outputs
    rfd : OUT STD_LOGIC;
    xn_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
    busy : OUT STD_LOGIC;
    edone : OUT STD_LOGIC;
    done : OUT STD_LOGIC;
    dv : OUT STD_LOGIC;
    xk_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
    xk_re : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    xk_im : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  );
END COMPONENT;

COMPONENT AD
    Port ( 
		CS_Clk : in STD_LOGIC; -- 48kHz Clock from Frequency divider goes to nCS
      nCS : out  STD_LOGIC; -- Chipselect negative active, Pin must be attachd to ADU-Hardware, gets clock of 48kHz
      Data_Out : out  STD_LOGIC_VECTOR (11 downto 0); -- Data to FFT
      Sample_Available : out STD_LOGIC; -- to TopModell
      CLK_out : out  STD_LOGIC; -- Clock to ADU (approx 2MHz) Pin must be attached to ADU-Hardware
      CLK_in  : in STD_LOGIC; -- Clock from Frequency divider (approx 2MHz)
      Data_In : in  STD_LOGIC -- Data from ADU-Hardware
         );
	END COMPONENT;
	
COMPONENT ANALYSIS
	    Port ( 
			  spectr_re : in  STD_LOGIC_VECTOR(11 downto 0);
           spectr_im : in  STD_LOGIC_VECTOR(11 downto 0);
           Red_LED : out  STD_LOGIC;
           Blue_LED : out  STD_LOGIC;
           Green_LED : out  STD_LOGIC
			);
	END COMPONENT;
	
begin
			
FFT : FFT_Core
	  PORT MAP (
		 clk => clk_fft,
		 start => start,
		 unload => unload,
		 xn_re => xn_re,
		 xn_im => xn_im,
		 fwd_inv => fwd_inv,
		 fwd_inv_we => fwd_inv_we,
		 scale_sch => scale_sch,
		 scale_sch_we => scale_sch_we,
		 rfd => rfd,
		 xn_index => xn_index,
		 busy => busy,
		 edone => edone,
		 done => done,
		 dv => dv,
		 xk_index => xk_index,
		 xk_re => xk_re,
		 xk_im => xk_im
	  );
	  
	  ADU : AD
			PORT MAP (
				CS_Clk   => adu_chip_select_sig, -- 48kHz Clock from Frequency divider goes to nCS
				nCS      => adu_nchip_select_sig, -- inverted chip select for ADU Hardware (48kHz)
				Data_Out => audio_sample_signal, -- Data to FFT
--				Sample_Available =>  sample_avail, 
				CLK_out  =>  adu_clock_pin_sig, -- Clock to ADU Hardwre (approx 2Mhz)
				CLK_in   =>  clk_adu_sig, -- Clock from Frequency divider
				Data_In  =>  data_from_adu_hw_sig
					);
					
	Spectrum_Analysis : ANALYSIS 
		    PORT MAP( 
			  spectr_re => xk_re,
			  spectr_im => xk_im,
			  Red_LED   => Red_LED,
			  Blue_LED  => Blue_LED,
			  Green_LED => Green_LED
			  );
	
	-----------------------------
	--------  TestBench  --------
	-----------------------------	
	   start				<=  start_TB;   
		unload_TB		<=  unload;
--		audio_sample_signal	<=  Data_in_TB;
		rfd_test 		<=  rfd;
		xn_index_test	<=  xn_index;
		busy_test 		<=  busy;
		done_test 		<=  done;
		xk_index_test  <=  xk_index;
		xk_re_test 		<=  xk_re;
		xk_im_test		<=  xk_im;
		fwd_inv			<= fwd_inv_TB;
		fwd_inv_we	 	<= fwd_inv_we_Tb;
		scale_sch 		<= scale_sch_TB;
		scale_sch_we	<= scale_sch_we_TB;


	sample_avail_sig     <= Sample_Avail;
					Res 		<= reset;
					
					
					
					
					
	----------------------------------------------------------------------------------------------------------------------------
	----------------------------------------------------------------------------------------------------------------------------
	-----------  Port Mapping Done  --------------------------------------------------------------------------------------------
	----------------------------------------------------------------------------------------------------------------------------
	----------------------------------------------------------------------------------------------------------------------------
	
	
	
	
	
	  -- Feeds the FFT with values
	LOAD_SAMPLES : process(Res, clk_50M, sample_avail)
			variable sample_vector : vector;
			variable sample_index : natural;
			variable xn_index_var: integer; --std_logic_vector(9 downto 0);
	
	begin
	
			-- Asynchronous Restart:
			if (Res = '1') then
				sample_vector := (others => "000000000000");
			--	start <= '0';
				unload <= '0';
				sample_index := 1; 	
				xn_re <= "000000000000";
				test 		<= '0';
				test2		<= '0';
				test3		<= '0';
				test4		<= '0';
				test3_sig <= '0';
				
			elsif (clk_50M'event and clk_50M = '1') then
--				test4 <= '1';
				-- waits for the ADU to sample a value. With the sample_avail-Flag going high a
				--       new value is loaded in the sample_vector
				if(sample_avail_sig = '1') then
						sample_vector(sample_index) := Data_in_TB;
						sample_index := sample_index + 1;
						test_count <= std_logic_vector(to_signed(sample_index,10));
						test <= '1';	
						
							if (sample_index = 1024) then
								sample_index := 1;
	--							start <= '1';
								test2 <= '1';
							--	start <= '0';  -- could cause problems since this would leed to unload <= '1' in the next if. probably needs to wait 1 or 2 clock cycles so busy can go high and stop the if
							end if;
				end if;
				
				
				if (rfd = '1') then
					xn_index_var := conv_integer(xn_index);
					xn_re <= sample_vector(xn_index_var);
					test_vector <= sample_vector(xn_index_var);
					test3 <= test3_sig;
					test3_sig <= not test3_sig;
					
					if (busy = '1') then
	--					start <= '0';
						test4 <= '1';
					end if;
					
				end if;

				
--				if (busy = '0' and start = '0') then
--					unload <= '1';
--				end if;
				
			end if;
			
	end process LOAD_SAMPLES;
	
	UNLOAD_SPECTRUM : process(unload)		
	begin
		if (unload = '1') then
		-- to Outputs and therefor to component "analysis"
			xk_index <= xk_index; 
			xk_re <= xk_re;
			xk_im <= xk_im;
		end if;
		
	end process UNLOAD_SPECTRUM;
	   

end Behavioral;

 

Any idea why the start signal which is initialised in the TestBench just would'nt reach the fft? Actually the rfd out should go high when the FFT-Core is ready to load data which is then started with setting the start bit high. But somehow rfd remains 0 all the time. 

 

Thanks again!

 

Regards,

 

Lenni

 

PS: Should I probably open a new thread for this question???

 

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Highlighted
Teacher
Teacher
3,810 Views
Registered: ‎08-14-2007

Re: In TestBench initialised values aren't "used" in ISim

Hi Lenni,

basically the code looks OK, start is going via start_TB directly to the FFT cores input.

 

Is the FFT_Core properly bound in the simulation?

(are you using the *.vhd wrapper with the Xilinxcorelib calls in your simulation?)

 

Check the design hierarchy in your simulator environment.

 

Have a nice simulation

  Eilert

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Observer
Observer
3,805 Views
Registered: ‎04-18-2012

Re: In TestBench initialised values aren't "used" in ISim

Hi!

 

I'm not really sure what you ment with "*.vhd wrapper with the Xilinxcorelib". All I did was including the FFT via New Source -> "IP Core" -> "FFT Core v7.1" Is there anything else I should do to include the FFT-Core???

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Observer
Observer
3,799 Views
Registered: ‎04-18-2012

Re: In TestBench initialised values aren't "used" in ISim

Most likely the error sits in front of the keyboard ... Once again it's true. I forgot to assign a clock for the FFT. For some reason I must have deleted it from the Component and the port map. Now as I declared a clk for the FFT-Core it works completly fine. 

 

Thank you guys for reading the code and taking the time. I really appreciated it.

 

Regards,

 

Lenni 

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