UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie jjsshimron
Newbie
2,194 Views
Registered: ‎03-03-2014

Initialising the XR16L788 Octal UART chip from my Virtex5 based custom FPGA board

Hello all,

 

I have been trying to initialise the Octal UART chip from Exar, XR16L788, from a simple verilog module to write and read to/fro a COM port in the PC (HyperTerminal) without success. I am not sure if my configuration information is sufficient enough for the UART chip.

 

I have used a state machine to set the MCR[7] bit high for making the pre select to select my desired baud rate of 115200. I next set the LCR[7] bit high to write the baud rate generator's division latch values, set the DLM in the next state, the DLL in the next and again reseting LCR[7] to enable RHR and THR in the next state. Now, I try to check if the LSR has the RHR data ready flag set (LSR[0] high) and I read from the RHR and based on what is input, I will output a particular set of values checking for the LHR empty flag in LSR (LSR[5] high) each time. Now, this I do as I have the FIFO disabled.

 

Doesn't this initialising cover initialising the Octal UART for simple applications without interrupts or am I missing something here?

 

I have used an Oscilloscope to check if my data is entering the chip properly as well. I am sending the configuration data in the frequency on which this particular UART chip runs (14.7MHz). Nothing seems to work. I will attach the state machine code for this here as well.

 

It would be really helpful to hear expert suggestions on this issue. I am really stuck here.

 

Best,

John

0 Kudos