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hrmr0406
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Registered: ‎10-09-2016

Inout Bypass Error

FPGA FAMILY : Spartan6

FPGA : XC6SLX75

inout_error1.png

 

In the interior of the FPGA, implementation of the Logic to become such as: Bypass.

DT is connected to the DSP side the Data Bus, D is connected to the Data Bus of different FPGAs the IC.

When you enter the DSP side Write Command, usually of Data is Masu Write, if you want to Read

Data is output for a while on Delay, I never read the Data that the DSP side firmly. (Attached figure)

Or not created in the above structure?

Or should the synchronization by placing the Flip Flop inside?

 

inout_error2.png

 

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hrmr0406
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Registered: ‎10-09-2016

In the picture of wave wn , rb is not correct. it's just probing error. this is read command.

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