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Registered: ‎04-01-2015

Input slew rate setting issue

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Hello,

Xilinx ISE : 14.4
Device: Spartan 6 (xc6slx9-2ftg256)

I am facing issue with ISE 14.4 for input SLEW RATE settings.

If we try to set the slew rate on input pin through PIN PLANNER GUI (Scrool Tab), GUI is not allowing to do so which is correct (As show in snapshot 1).
 
But, if we go to next section of GUI as shown in [snapshot 2] (IO property block) and modified input slew rate setting (Showing in Snapshot 3), it reflects in the .UCF file (Snapshot 4)  and passes all theprocess (Translate, MAP and PAR) without any warnings or errors.

This behaviour of tool is incorrect becuase as per my understanding we cannot set the slew rate on input pins.

Kindly provide me the information rather thats the tool issue or we can change the input slew rate.


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Snapshot 1 .png
Snapshot 2.png
Snapshot 3.png
Snapshot 4.png
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Historian
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Registered: ‎02-25-2008

Re: Input slew rate setting issue

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@siddesh.botadra wrote:

Hello bassman59

 

As per my understanding from below wiki article, slew rate is only applicable to the output pins of any device (in our case it is FPGA). 

 

http://en.wikipedia.org/wiki/Slew_rate

 

Input pin does't care about slew rate. So here issue Xilinx ISE tool does't allow to set slew on input pin (through GUI in snapshot 1) but it do accept slew rate setting through .ucf and IO propertry editor which wrong.

 

Also tool does't give any warning to user regarding the input slew rate.

 


So, what's the problem? The setting is simply ignored. Anyone who understands electronics realizes that slew rate for an input is meaningless.

 

Although I have no idea what the tools with do with a specific slew rate setting for an input, because I've never done it. Maybe a warning?

----------------------------Yes, I do this for a living.

View solution in original post

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Historian
Historian
1,951 Views
Registered: ‎02-25-2008

Re: Input slew rate setting issue

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ummm, THINK for ONE MINUTE on why you cannot set a slew rate constraint for an INPUT.

 

Go ...

----------------------------Yes, I do this for a living.
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Highlighted
1,912 Views
Registered: ‎04-01-2015

Re: Input slew rate setting issue

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Hello bassman59

 

As per my understanding from below wiki article, slew rate is only applicable to the output pins of any device (in our case it is FPGA). 

 

http://en.wikipedia.org/wiki/Slew_rate

 

Input pin does't care about slew rate. So here issue Xilinx ISE tool does't allow to set slew on input pin (through GUI in snapshot 1) but it do accept slew rate setting through .ucf and IO propertry editor which wrong.

 

Also tool does't give any warning to user regarding the input slew rate.

 

 

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Highlighted
Historian
Historian
1,899 Views
Registered: ‎02-25-2008

Re: Input slew rate setting issue

Jump to solution

@siddesh.botadra wrote:

Hello bassman59

 

As per my understanding from below wiki article, slew rate is only applicable to the output pins of any device (in our case it is FPGA). 

 

http://en.wikipedia.org/wiki/Slew_rate

 

Input pin does't care about slew rate. So here issue Xilinx ISE tool does't allow to set slew on input pin (through GUI in snapshot 1) but it do accept slew rate setting through .ucf and IO propertry editor which wrong.

 

Also tool does't give any warning to user regarding the input slew rate.

 


So, what's the problem? The setting is simply ignored. Anyone who understands electronics realizes that slew rate for an input is meaningless.

 

Although I have no idea what the tools with do with a specific slew rate setting for an input, because I've never done it. Maybe a warning?

----------------------------Yes, I do this for a living.

View solution in original post

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