04-22-2015 12:58 AM
I am currently performing a board design where I have to interface several SPI slaves to a Zynq XC7Z020. Reading material regarding SPI just gives me a general knowledge about the protocol and its settings, but I struggle with understanding and finding information regarding interfacing different types of slaves on the same SPI bus.
The first issue is word length; this seems to be set as a fixed length in the SPI master, while the different slaves may operate with different lengths from each other. Are there any considerations that must be taken regarding word length? For instance when interfacing a slave with a fixed 16-bit interface alongside with another one with 32 bits on the same bus?
The second issue is the clock line maximum frequency. The slaves have different limitations here. Is it possible to vary the maximum clock frequency for a given slave, or must the SPI master be set at a fixed frequency, making it impossible to interface slaves of different clock frequencies? A thought I have to solve this issue, is to use different masters for different SPI bus clock speeds, essentially making 2-3 SPI buses with different clock rates for multiple slaves on each bus, but this would of course require more FPGA I/O which is sparse in my project.
The third issue is the SPI modes. This may be the least of my problems, as many of the slaves operates in the same mode, either 1 or 3. Is it however possible to change mode within the master depending on which slave that is selected?
Any answer regarding any of the above questions, or any hints and tips for making my final design decisions on this matter is much appreciated.
Struggling EE student
04-22-2015 06:33 AM
Typically you would set up the master to run at the narrowest data width and use multiple word transactions to deal with wider slaves. Also typically you'd run the clock at the rate of the slowest device. Otherwise it's possible that the slow device could get into an unknown state even if its chip select is not active when the clock is running faster than its design spec.
If you really want to make a SPI master that runs in different widths and at different frequencies for different external devices, you could always code that yourself in the fabric logic. If you really have to run some SPI device much faster than another, it's also a good idea to separate the SPI buses rather than sharing with a slow device.
04-22-2015 08:17 AM
The great thing about FPGAs is that you can have as many SPI (or whatever) ports as you like.
So rather than having a one-master-fits all, use one per slave or slave group.