07-02-2017 11:54 PM
Hi i wanted to encrypt by RTL,is it possible with ISE because i wanted to generate bitfile with encrypted RTL for VIRTEX6 devices so as vivado does not support 6 devices how can i generate in ISE.can you please help me out.
07-03-2017 04:40 AM
Xilinx FPGAs support several bitstream encryption methods including AES, HMAC and DNA. These methods are detailed in the FPGA's respective configuration user guide (UG360) found on Xilinx.com.
We strongly urge customers to read the configurations user guide to familiarise themselves with where Xilinx stands on bitstream security and what available options there are as well as information on how to implement them.
Please refer below useful reference
07-03-2017 08:10 AM - edited 07-03-2017 08:17 AM
Yes it is possible to use encryption in ISE with the Virtex-6, Answer Record 52881 has information on this.
Also Answer Record 39389 has good information.
Please mark an answer "Accept as solution" if a post has the solution to your issue.
07-03-2017 09:08 PM
@abhishek7- Did your query answered? If yes, please close the thread by clicking on “Accept as Solution” tab for that particular reply posts which were more helpful for you. That will be helpful for other users
FYI: To know how to generate an encrypted bitstream and how do I program the encryption keys into the FPGA please refer below answer record
The following Answer record.https://www.xilinx.com/support/answers/39389.html discuss Frequently Asked Questions (FAQ) for bitstream encryption
Additionally below application notes helps provides anti-tamper (AT) guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system.
07-05-2017 12:44 AM
@abhishek7-- Please let us know if you have any further queries? We will try to help with our best efforts.
07-12-2017 09:33 PM
thanks for your all the info you provided but i specifically asked about the design encryption,means RTL code encryption not the bitstream, i want to deliver RTL to the customer so how would i encrypt the source code(RTL) I have successfully done in VIVADO but as vivado doesnot support virtex6 devices so is there any possibility to encrypt my RTL in ISE???
09-10-2017 08:35 AM
is it available a version of Application Note 780 for Virtex6 FPGA ?
The application note implements bitstream security through the use of DS2432 chip, but I can’t find source code for Virtex6 FPGA.
Can you help me to find it?
09-12-2017 12:36 AM - edited 09-12-2017 12:37 AM
Hi @abhishek7, unsure if you ever got to the bottom of this however, unfortunately not. It is not possible to encrypt RTL in ISE, only since Vivado 2016.3 is this possible. While Xilinx did have an encryption tool (for ISE), it was only shared with very select partners unde
Some customers found it sufficient to provide the netlist using the NGC format. This is, however, not an encrypted format. Using netgen, a structural netlist can be extracted from the NGC.
Most customers are only concerned about their IP users having access to the RTL code that describes the behavior of the core. If they are not concerned about the possibility of generating structural netlist, maybe you could provide the core via NGC netlist. This is the solution most of the Alliance IP use.
To do this, synthesize the module in question while disabling "Insert I/O Buffers" property in XST.