cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
3,073 Views
Registered: ‎03-20-2017

Is encryption possible in ISE?

Hi i wanted to encrypt by RTL,is it possible with ISE because i wanted to generate bitfile with encrypted RTL for VIRTEX6 devices so as vivado does not support 6 devices how can i generate in ISE.can you please help me out.

0 Kudos
7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
3,054 Views
Registered: ‎08-01-2012

Xilinx FPGAs support several bitstream encryption methods including AES, HMAC and DNA. These methods are detailed in the FPGA's respective configuration user guide (UG360) found on Xilinx.com.

We strongly urge customers to read the configurations user guide to familiarise themselves with where Xilinx stands on bitstream security and what available options there are as well as information on how to implement them.

Please refer below useful reference 

https://www.xilinx.com/support/documentation/application_notes/xapp780.pdf  &

 

http://www.xilinx.com/support/documentation/user_guides/ug360.pdf 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Highlighted
Moderator
Moderator
3,034 Views
Registered: ‎04-24-2013

Hi @abhishek7,

 

Yes it is possible to use encryption in ISE with the Virtex-6, Answer Record 52881 has information on this.

 

https://www.xilinx.com/support/answers/52881.html

 

Also Answer Record 39389 has good information.

 

https://www.xilinx.com/support/answers/39389.html

 

Bitgen_Opt_201211141357243944.png

 

Best Regards
Aidan

 

--------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
2,981 Views
Registered: ‎08-01-2012

@abhishek7- Did your query answered? If yes, please close the thread by clicking on “Accept as Solution” tab for that particular reply posts which were more helpful for you. That will be helpful for other users

 

FYI: To know how to generate an encrypted bitstream and how do I program the encryption keys into the FPGA please refer below answer record

https://www.xilinx.com/support/answers/52881.html

 

The following Answer record.https://www.xilinx.com/support/answers/39389.html discuss Frequently Asked Questions (FAQ) for bitstream  encryption

 

Additionally below application notes helps provides anti-tamper (AT) guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system.

https://www.xilinx.com/support/documentation/application_notes/xapp1084_tamp_resist_dsgns.pdf 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

Highlighted
Xilinx Employee
Xilinx Employee
2,924 Views
Registered: ‎08-01-2012

@abhishek7-- Please let us know if you have any further queries?  We will try to help with our best efforts. 

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Highlighted
Observer
Observer
2,856 Views
Registered: ‎03-20-2017

hi @umamahe

 thanks for your all the info you provided but i specifically asked about the design encryption,means RTL code encryption not the bitstream, i want to deliver RTL to the customer so how would i encrypt the source code(RTL) I have successfully done in VIVADO but as vivado doesnot support virtex6 devices so is there any possibility  to encrypt my RTL in ISE???

 

Regards

abhishek

0 Kudos
Highlighted
Observer
Observer
2,463 Views
Registered: ‎09-08-2017

Dear all,

is it available a version of Application Note 780 for Virtex6 FPGA ?

 

The application note implements bitstream security through the use of DS2432 chip, but I can’t find source code for Virtex6 FPGA.

Can you help me to find it?

 

Best regards

0 Kudos
Highlighted
Moderator
Moderator
2,426 Views
Registered: ‎02-07-2008

Hi @abhishek7, unsure if you ever got to the bottom of this however, unfortunately not. It is not possible to encrypt RTL in ISE, only since Vivado 2016.3 is this possible. While Xilinx did have an encryption tool (for ISE), it was only shared with very select partners unde

Some customers found it sufficient to provide the netlist using the NGC format. This is, however, not an encrypted format. Using netgen, a structural netlist can be extracted from the NGC.

Most customers are only concerned about their IP users having access to the RTL code that describes the behavior of the core. If they are not concerned about the possibility of generating structural netlist, maybe you could provide the core via NGC netlist. This is the solution most of the Alliance IP use.

To do this, synthesize the module in question while disabling "Insert I/O Buffers" property in XST.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos