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gmstomm
Contributor
Contributor
2,293 Views
Registered: ‎03-31-2014

Issue Coping Array of Arrays

Hi Folks!

 

First, Thanks for your support and Merry X-Mass!

 

I have been writing Memory interfaces and test programs to get familiar with VHDL. Currently working on a AXI-Lite BRAM program with 2048, 32 bit words, being addressed with a 15 bit address through a single port.  In my Test Bench, I have a section that reads binary data text files and loads data sets into array of arrays.

 

I have a "DRIVER" design file that has the following;

 

In the Library area;

 

   package Data_PKG is
   type Data_Array_PKG is array(natural range <>) of std_logic_vector(31 downto 0);-- Unconstrained array!!!!
   end package;
   --
   library work; use work.Data_PKG.all;

 

In the Entity declaration area;

 

entity AXI_LITE_BRAM_Mem_Driver is
Generic (
Mem_Width : INTEGER := 32;
Mem_Depth : INTEGER := 2048;
Add_Bus_Width : INTEGER := 15;
Num_Words : INTEGER := 2048);

Port (
RE_WRT : in STD_LOGIC; -- Read =0, Write = 1
Start_Address : in STD_LOGIC_VECTOR ( Add_Bus_Width-1 downto 0);
Write_Data &colon; in Data_Array_PKG(0 to Num_Words-1);-- Using Package Def of Array of Arays!
Read_Data &colon; out Data_Array_PKG(0 to Num_Words-1);-- out array(0 to Num_Words-1) of std_logic_vector( Mem_Width-1 downto 0);
Start : in STD_LOGIC;
Done : out STD_LOGIC:='0';
CLK_IN : in STD_LOGIC;
RESET_IN : in STD_LOGIC);
end AXI_LITE_BRAM_Mem_Driver;

 

In the Test Bench,

 

In the Library Area;

 

   LIBRARY work;
   USE work.BMG_TB_PKG.ALL;
   USE work.Data_PKG.all;

 

In the Signal Def Area;

 

   SIGNAL tb_Write_Data&colon; Data_Array_PKG(0 to 2047);-- Using Package Def of Array of Arrays!
   SIGNAL tb_Write_Data1,tb_Write_Data2, tb_Write_Data3,tb_Write_Data4: Data_Array_PKG(0 to 2047);
   SIGNAL tb_Read_Data &colon; Data_Array_PKG(0 to 2047);

 

In the Component declarition area;

 

component AXI_LITE_BRAM_Mem_Driver
Generic (
Mem_Width : INTEGER := 32;
Mem_Depth : INTEGER := 2048;
Add_Bus_Width : INTEGER := 15;
Num_Words : INTEGER := 2048);

Port (
RE_WRT : in STD_LOGIC; -- Read =0, Write = 1
Start_Address : in STD_LOGIC_VECTOR ( Add_Bus_Width-1 downto 0);
Write_Data &colon; in Data_Array_PKG(0 to Num_Words-1);-- Using Package Def of Array of Arays!
Read_Data &colon; out Data_Array_PKG(0 to Num_Words-1);
Start : in STD_LOGIC;
Done : out STD_LOGIC;
CLK_IN : in STD_LOGIC;
RESET_IN : in STD_LOGIC);
end component;

 

I read in  tb_Write_Data1 ,tb_Write_Data2,  tb_Write_Data3, tb_Write_Data4 from the Text Files.

 

These data sets look perfect in the simulation!

 

Then, in the TB code I have;

 

  tb_Write_Data <= tb_Write_Data1; 

 

 

The data from tb_Write_Data[0] to  tb_Write_Data[333] matches the tb_Write_Data1.

 

At tb_Write_Data[334] and above, I get "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU".

 

I have looked for the issue, tried different data sets, and examined the Elabroated Design for multiple driver issues. I cannot see any issues. 

 

Anyone know why this might be happening????

 

Thanks!

 

gmstomm

 

 

 

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4 Replies
gszakacs
Professor
Professor
2,259 Views
Registered: ‎08-14-2007

Well it could be a tool limitation (bug).  What simulator are you using?  Vivado?  ISE ISIM? ModelSim?

 

Have you checked that tb_Write_Data1 still has valid data above index 333 after the assignment to tb_Write_Data?

 

If you change the simple assignment to a loop from 0 to 2047 assigning individual elements, does this work?

-- Gabor
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gmstomm
Contributor
Contributor
2,223 Views
Registered: ‎03-31-2014

Hi Gabor!

 

I am using Vivado's Simulator.

 

The Source array is complete and correct.

 

I tried using a loop and got the same results.

 

Any other ideas?

 

Best Regards,

 

gmstomm

 

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gszakacs
Professor
Professor
2,209 Views
Registered: ‎08-14-2007

My original thought was that Vivado has some memory limitation for storage of arrays, however if that were the case, then the original array would also have the problem.  Since that is not the case, then there could still be a limitation for total array storage, although it seems unlikely that it would fail at an odd number of words.  Another thought was that the destination array was also driven by another process, but then you should get 'X' instead of 'U'.  Honestly this seems like a bug.  For behavioral simulation you should be able to try Isim from ISE 14.7 to see if that has a similar issue.  Otherwise I'd suggest trying to consolodate down to a minimum project that shows the problem and post it so someone can take a look at it.  Also see if you can get access to another simulator like ModelSim, which is unlikely to show the same issue unless there is in fact a problem with your code.

-- Gabor
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gmstomm
Contributor
Contributor
2,116 Views
Registered: ‎03-31-2014

Gabor,

 

I have not had time to completely nail this issue. However, here is a point of interest. I modified the For-Next Loop as follows;

 

For ADDR_CTR in 0 to 2047 loop
tb_Write_Data(ADDR_CTR) <= std_logic_vector(to_unsigned(ADDR_CTR, 32)); 
end loop;

 

which writes the 32 bit binary equivalent of the loop counter.

 

This worked and filled all 2048 locations correctly. FYI, I did not stop the text file reads. So all 5 Array oy Arrays were filled correctly.

 

This gave me a working data set so I went on to troubleshoot other issues in my project.

 

Happy New Year!

 

gmstomm.

 

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