03-14-2017 08:21 AM
I must import the code developed for a Virtex 6 to interface the ADC outputs in the JESD204B standard, on a Kintex 7.
I modified the code and the ucf file to implement it on the demoboard MC705.
The Synthesize and the translate steps are ok, but the map fails.
The error that is on all input lines is:
Pack:1107 - Pack was unable to combine the symbols listed below into a
single IOB component because the site type selected is not compatible.
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
IOB was chosen because the IO contains symbols and/or properties consistent
with input, output, or bi-directional usage and contains no other symbols or
properties that require a more specific IO component type. Please double
check that the types of logic elements and all of their relevant properties
and configuration options are compatible with the physical site type of the
PAD symbol "jesd_data_lane7_p" (Pad Signal = jesd_data_lane7_p)
BUF symbol "jesd_data_lane7_p_IBUF" (Output Signal = jesd_data_lane7_p_IBUF)
Component type involved: IOB
Site Location involved: F6
Site Type involved: IPAD
I have checked the ucf to find the IO pins with incompatible standard connected on the bank of the JESD204 input (117 and 118) but there aren't others pins.
i tried to declare the IOSTANDARD=LVDS_25, but nothing
I tried to insert a IBUFDS_DIFF_OUT also, but nothing.
Can you help me?
03-14-2017 11:52 AM
03-21-2017 01:56 AM
It is recommended to use Vivado as bug fixes will be done only in it and ISE will not be having any bug fixes
You can still use ISE if you have a strong reason for not to migrate with the latest version of core present in ISE14.7