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Visitor
Posts: 3
Registered: ‎10-12-2017
Accepted Solution

Kintex-7 KC705 XADC Block

Hi,

 

I would like to use the XADC Block on my FPGA (KC705 - using Vivado 2017.2) and I am new at the VHDL programming. I read a guide about XADC but I could not use it (https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf).

Can you share with me an example code (VHDL) about using XADC Block? 

 

Thank you all.


Accepted Solutions
Highlighted
Moderator
Posts: 8,793
Registered: ‎02-27-2008

Re: Kintex-7 KC705 XADC Block

Go to the wizard,

 

Import the IP.  There will be options while importing.

 

Or, UG 480 has an example design at the end in verilog.  Vivado supports mixed code, so you do not need VHDL to get it working.

 

It looks like it is best to use the wizard to instantiate the XADC, however, as that appears to be the easiest and best way today.  I have always used the example verilog (still do in 20nm and 16nm parts).

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post


All Replies
Moderator
Posts: 8,793
Registered: ‎02-27-2008

Re: Kintex-7 KC705 XADC Block

[ Edited ]

PG091,

 

Chapter 5.

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 3
Registered: ‎10-12-2017

Re: Kintex-7 KC705 XADC Block

Thank you but I asked for VHDL example. That code is written in Verilog if there is no VHDL code I will generate that code VHDL.

Visitor
Posts: 3
Registered: ‎10-12-2017

Re: Kintex-7 KC705 XADC Block

And there is not that kind of file.

(<project_name>/<project_name>.srcs/sources_1/ip/<component_name>/example_design/<component_name>_exdes.vhd)

Untitled.png
Highlighted
Moderator
Posts: 8,793
Registered: ‎02-27-2008

Re: Kintex-7 KC705 XADC Block

Go to the wizard,

 

Import the IP.  There will be options while importing.

 

Or, UG 480 has an example design at the end in verilog.  Vivado supports mixed code, so you do not need VHDL to get it working.

 

It looks like it is best to use the wizard to instantiate the XADC, however, as that appears to be the easiest and best way today.  I have always used the example verilog (still do in 20nm and 16nm parts).

Austin Lesea
Principal Engineer
Xilinx San Jose