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Visitor logiznam
Visitor
3,313 Views
Registered: ‎10-08-2012

LVDS data transfer from ADC to FPGA

Hi all,

 

I would like to use in my design AD9272. Timing diagrams you can find on page 10:

 

http://www.analog.com/static/imported-files/data_sheets/AD9272.pdf

 

Target device:  xc6slx45-3csg324, conversion @80MHz (Frame_clk=80MHz , DDR bit_clk=480MHz)

 

I have found similar problem described in Xapp774.pdf . I've made the deserializer very similar to that one as on Fig.3.

However, the multiplexer is not used in my design. I simply align the output bits from the shift registers in a right order before registering them by Frame_clk in the 12-bit output register (rg12v). Design:

 

http://www.fotosik.pl/pokaz_obrazek/pelny/2283182cdb320bb7.html

http://www.fotosik.pl/pokaz_obrazek/pelny/7afa677f6aba1b89.html

 

Functional simulation is OK. However post P&R simulation gives sometime 'X' on some output bits even at very low frequency (10-20MHz). What are the reasons? Any suggestions how to improve my design are very welcome.

 

Thanks,

 

Stachu

 

 

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2 Replies
Scholar austin
Scholar
3,300 Views
Registered: ‎02-27-2008

Re: LVDS data transfer from ADC to FPGA

Have you been following this thread?

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Xilinx-ISE-Simulator-assigns-X-value-to-the-output/td-p/29425

 

I think the causes of 'X' in the simulations are all discussed, and suggestions for their resolution.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Highlighted
2,664 Views
Registered: ‎03-09-2014

Re: LVDS data transfer from ADC to FPGA

Hi,

Can you give me your project vhdl. i also want to simulate the data transfer between ADC 12 bit and FPGA kit with LVDS. my email is thanghapfiev@gmail.com

many thanks! ^^

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