11-29-2016 11:15 AM
I have implemented a simple program
ibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity TDC_EvaluationSignal is Port ( Refclk : in STD_LOGIC; StopSignal : out STD_LOGIC; TDCrefClk : out STD_LOGIC); end TDC_EvaluationSignal; architecture Behavioral of TDC_EvaluationSignal is signal StopSignalReg: STD_LOGIC := '0'; signal TDCrefClkReg: STD_LOGIC := '0'; signal counterReg: integer := 0; signal TDCrefClkRegPrev : STD_LOGIC := '0'; begin Generateclock : process (RefClk) begin if (RefClk= '1' and RefClk'event) then TDCrefClkReg <= not TDCrefClkReg; counterReg <= 1; if (counterReg =1) then counterReg <= 0; StopSignalReg <= '1'; end if; end if; if (RefClk= '0') then StopSignalReg <= '0'; end if; end process; StopSignal <= StopSignalReg; TDCrefClk <= TDCrefClkReg; end Behavioral;
In simulation I can see the signal, but after flashing in hardware I can only see TDCrefclk not stopSignal.
further I take this signal to generate LVDS output
But stil these LVDS outptu is not available at the set PINS
here is the pin configuration
There is a signal on Fclk and TDCcrefCk but not stop_signal. stop_signal_ p and TDCClk_p
May I know what wrong I am doing. How can I proceed ?
11-30-2016 07:56 AM
11-29-2016 11:31 AM
if (RefClk= '0') then StopSignalReg <= '0'; end if;
These lines are causing the trouble for you. Your description of StopSignal register does not conform to synthesizable subset. You need to change it so that you update it only on one edge of the clock.
11-30-2016 12:05 AM
Thank you for pointing out the my mistake.
I would like to know if I want to initiate a signl and rising edge of clock and then want to make it zero at falling edge of the clock.
how should I proceed ?
11-30-2016 02:04 AM
I changed the code to
Generateclock : process (RefClk) begin if (RefClk= '1' and RefClk'event) then TDCrefClkReg <= not TDCrefClkReg; counterReg <= 1; if (counterReg =1) then counterReg <= 0; StopSignalReg <= '1'; StopSignalReg <= '0' after 500ns; end if; end if;
still it dont work
May I have your suggestion what should I do to get this waveform
11-30-2016 07:56 AM