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msh
Voyager
Voyager
4,895 Views
Registered: ‎10-31-2016

LVDS pin assignments

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Hi, 

 

I am trying to implement LVDS output in zynq 7020. 

In the IO bank 35 , I tried to to use a PIN as LVDS but there is always an error, as from the same bank there is another pin been used for default config with 3.3 voltage of VCCO .

 

[DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
START_PULSE_I (LVCMOS33, requiring VCCO=3.300) and StopSignal_P[0] (LVDS_25, requiring VCCO=2.500)

 

I read the below link 

https://www.xilinx.com/support/answers/64450.html

 

but it also didnt remove the error. 

 

Do I have to do some extra ? 

 

Please let me know how can I proceed

 

thanks 

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gnarahar
Moderator
Moderator
8,495 Views
Registered: ‎07-23-2015

@msh As Ashish mentioned, LVDS outputs require VCCO to be at the respective Voltage level i.e. 1.8V for LVDS (HP Bank) and 2.5V for LVDS_25. 

 

LVDS Inputs though can be placed in bank with VCCO not matching to the required level with some conditions. 

 

Go through this AR which will pretty much explain the scenarios https://www.xilinx.com/support/answers/43989.html

 

In your case, you need to move LVDS_25 outputs to another Bank with 2.5V VCCO

 

 

- Giri
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4 Replies
ashishd
Xilinx Employee
Xilinx Employee
4,891 Views
Registered: ‎02-14-2014

Hello @msh,

 

There are certain rules which needs to be followed while combining IOSTANDARDS in same bank. Please check page #97 from below UG

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Regards,
Ashish
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msh
Voyager
Voyager
4,880 Views
Registered: ‎10-31-2016

Hello @ashishd

 

Thank you for me directing to the reference. 

 

According to the combination list, the output or input of different standard can be combine only if they have same VCCO. 

so does that mean I should use another IO bank for LVDS ? or there any other way ? 

 

 

Thank you 

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ashishd
Xilinx Employee
Xilinx Employee
4,873 Views
Registered: ‎02-14-2014

Hello @msh,

 

Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. But you need to consider important criteria mentioned in Note 1 (page #100 ) from UG mentioned in my earlier reply. If this criteria is not followed, then you should consider using another bank.

Regards,
Ashish
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gnarahar
Moderator
Moderator
8,496 Views
Registered: ‎07-23-2015

@msh As Ashish mentioned, LVDS outputs require VCCO to be at the respective Voltage level i.e. 1.8V for LVDS (HP Bank) and 2.5V for LVDS_25. 

 

LVDS Inputs though can be placed in bank with VCCO not matching to the required level with some conditions. 

 

Go through this AR which will pretty much explain the scenarios https://www.xilinx.com/support/answers/43989.html

 

In your case, you need to move LVDS_25 outputs to another Bank with 2.5V VCCO

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

View solution in original post