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muffinman121
Visitor
Visitor
2,175 Views
Registered: ‎01-30-2017

MCB Pin configuration (Spartan 6 LX 45 324ball bga)

Hi

 

I'm currently writing my Master thesis and for the project I'm doing a data collection circuit. Due to time constraints I need to make a PCB before I write the (VHDL) code for the FPGA. But here I've run into trouble. I apologize if I missed something obvious or another post/user guide treats the problem (but couldn't find any?). I'm not very experienced in the use of FPGAs.

 

It seems that the MCB (Memory Control Block) will connect to some predetermined pins on the FPGA, but I can't seem to figure out which pins are going to be used. I have only found the two pins for the RZQ and ZIO but I can't seem to find any other pin requirements such as for the CLK, address and data? Do they connect to to any IOs (CLK pin of course to a pin with clocking hardware) in the bank of the MCB (bank 3 in my design) or do they also have pre determined pins?

 

From the Xilinx UG393 it seems like all signals have pre determined pins from the following quote "The Memory Interface Generator (MIG) tool in the Core Generator software generates the specific pin assignments for each MCB." (page 63).

 

If anyone knows where to find the information on which pins any signal connects to or where to find the information it would be greatly appreciated.

 

 

Specs:

*Xilinx ISE 13_2_4

*VHDL
*Spartan 6 (XC6SLX45-3CSG324I)

* Using Bank 3 MCB

*DDR2 RAM (Micron Technology Inc. MT47H128M16RT-25E:C)

 

Any help is greatly appreciated

Best regards

A confused student

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yenigal
Xilinx Employee
Xilinx Employee
2,143 Views
Registered: ‎02-06-2013

Hi

 

Refer below link for the MCB pinout information

 

https://www.xilinx.com/support/packagefiles/s6packages/6slx45csg324pkg.txt

 

Pin description can be found in below link

 

https://www.xilinx.com/support/documentation/user_guides/ug385.pdf

Regards,

Satish

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muffinman121
Visitor
Visitor
2,092 Views
Registered: ‎01-30-2017

Hi,

 

Thank you for your help :)

 

I found that when generating an IP core in xilinx ISE a .ucf file is generated under the ip core folder (<project name>\ipcore_dir\<core name>\example_design\par\example_top.ucf). This file contains the information i need.

Further i found this youtube video going through what seems to be the whole process (if anyone should seek the information in the future):

https://www.youtube.com/watch?v=43agTYExgSQ

 

 

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