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Observer matt_marti09
Observer
3,621 Views
Registered: ‎08-27-2012

ML605 DDR3 Clock Change

   I am preparing to write a system which outputs stored data from DDR3 external memory to ethernet into matlab.  I have already setup the ethernet to FPGA and recieve data fine.  I am running low on FPGA overall memory so I would like to avoid using a FIFO or bRAM system if possible.  For this reason, I decided to change the DDR3 read clock speed to the speed of the ethernet.  This way I would be able to avoid changing clock domains.  I did not write the code for DDR3 in our system but the documentation is confusing especially with the extent of clocks that are used.  I tried regenerating the DDR3 code in core gen with the clock speed to ethernet as I would like but double the speed since it is DDR.  Core gen would not allow the speed of 2x133MHz that I needed.  Is there a way to change the DDR read clock to a speed that I like.  The documentation seems to point to the fact that the clock must be half the speed as the memory clock which is currently 400MHz.  This is why I tried to change the mem clock to 266MHz without any luck.  Any suggestions? 

 

Thanks,

Matt Martinez

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2 Replies
Scholar austin
Scholar
3,599 Views
Registered: ‎02-27-2008

Re: ML605 DDR3 Clock Change

Matt,


The frequency must match the capability of the memory type,

 

http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf (page 25, Figue 1-12),

 

and it needs to be compatible with the FPGA device.


Since you wish to go slower, that should be easy for the FPGA, but may be an issue for the DDR3 SODIMM module.

 

Check that one out.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer matt_marti09
Observer
3,578 Views
Registered: ‎08-27-2012

Re: ML605 DDR3 Clock Change

Thanks!

Actually one of the first things I tried was to regenerate the core.  I found that I was not able to get two times the speed of the clock I needed. I needed a clock speed of 133MHz therefore I tried using 266MHz but it would not even let me type in the corresponding period based on my fpga model and speed.  I decided just to use a FIFO but so far it doesn't seem like I will have enough memory.

 

Thanks for your time,

Matt Martinez

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