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thisisobul
Visitor
Visitor
1,810 Views
Registered: ‎11-05-2014

Multiple drivers error while connecting mmcm clocks to MIG

hai

i am using ml605 board, and i want to interface ddr3 ram with MIG, the MIG requires two clocks (200,400 MHz). so i generated from MMCM and interfaced to MIG then the error comming as the both clock lines has multiple drivers. i tried to solve by seeing other threads but its not happened. please give me solution

 

i tried the mmcm with and without output buffers

if i put output buffer error comming as multiple buffers in one line

if i remove buffer then error comming as line has multiple drivers

 

 

thanks...

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vuppala
Xilinx Employee
Xilinx Employee
1,807 Views
Registered: ‎04-16-2012

Hello,

 

I suggest you to check the Technology schematic when the error was multiple buffers in one line.

Then write the buffer_type constraint on that specific net. 

If using ISE, see the section buffer_type in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

If using Vivado, see http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf

 

Thanks,

Vinay

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smarell
Community Manager
Community Manager
1,797 Views
Registered: ‎07-23-2012

Refer to the below threads for some inputs in resolving this error-

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Spartan-6-PLL-gt-MCB-Buffer-in-Series-problem/td-p/481160

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/NgdBuild-455-Multiple-drivers-error-related-with-DDR2-clocking/td-p/484152
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vsrunga
Xilinx Employee
Xilinx Employee
1,796 Views
Registered: ‎07-11-2011

Hi,

 

You can use MMCM with in MIG and derive required clocks so that it save additional MMCM. 

Please check below link and follow the suggestions for modifying the RTL

http://www.xilinx.com/support/answers/35242.html

 

http://www.xilinx.com/support/answers/43559.html

 

 Hope this helps

 

-Vanitha

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