UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
5,163 Views
Registered: ‎05-01-2016

NAND flash NV-DDR2 Interface with k7_325t fpga

Hi

  Recently, I designed NAND flash NV-DDR2 InterfaceIn fpga inside, rtl code is as follows

 IOBUFDS #(                     

          .IBUF_LOW_PWR("TRUE"),  //Low Power - "TRUE", High Performance = "FALSE" 

          .IOSTANDARD("DEFAULT"), //// Specify the I/O standard   

          .SLEW("FAST") // Specify the output slew rate 

       ) OBUFDS_DQS (          

          .IO   (nand_dqs_p      ),

          .OB   (nand_dqs_n      ),

          .O    (nand_dqsin      ),

          .I    (nand_dqs_ddr   ),

          .T    (io_ctrl     ) 

       );                          

 

always @( posedge nand_dqsin or posedge rst )begin  

    if ( rst )begin                              

        dqs_cnt                 <=  {8{1'b0}} ;     

    end

     else if(cnt_clr) begin

              dqs_cnt                 <=  {8{1'b0}} ; 

       end                                        

    else ifwr_dqs_en begin                                       

dqs_cnt                 <= dqs_cnt + 1;

       end

end

 io_ctl signal control timing is right .

I found a problem, dqs_cnt and number of dqs signal that oscilloscope detected is unequal

dqs differential type, pin type is IO, level property DIFF_SSTL18_II, dqs pulse of 83MHz

Finally, I put IOBUFDS into single-ended, the problem is the sameFinally, I change the frequency (dqs frequency becomes 41.5MHz), there is no problemWhat causes this problem?thanks。

0 Kudos
1 Reply
3,239 Views
Registered: ‎08-25-2015

Re: NAND flash NV-DDR2 Interface with k7_325t fpga

Hi Liuyong,

 

 

As per timing diagram when DQS is returned from toggling, it will be '1' state after last falling edge of valid DQS.

This may cause the issue.

 

 

0 Kudos