11-12-2016 05:54 AM
I am new to this community and familiar with FPGA and its languages (VHDL,VERILOG). I am facing some problem in MIG 7 Series Memory Controller. I designed MIG (DDR3 SDRAM) with core tool generator for (Artix 7). I just want to run example_design with Modelsim, to see how it works. I am following UG586.pdf manual and some readme.txt files for "how to achieve simulation". But I don't think so I am on right track. The Track I am following, correct me if I am wrong.
Am I right ? I am working on these things for last two weeks. I apologize if I sound newb.
Thanks in Advance
11-13-2016 07:52 PM
Yes after mapping the simulation libraries and running the sim.do file in the simulation directory should finish the simulation with out any issue's.
What is the error you are seeing following this flow?
which version of ISE and Modelsim are you using?
11-13-2016 08:21 PM - edited 11-13-2016 08:22 PM
You need to just compile libraries for Modelsim using compxlib in ISE and then follow the below steps
a) The user should invoke the Modelsim simulator GUI.
b) Change the present working directory path to the sim folder (ipcore_dir\ip_name\example_design\sim).
at Modelsim prompt, type the following command to
change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim prompt, type the following command:
d) To exit simulation, type the following command at Modelsim prompt:
11-24-2016 12:27 PM
Thank you for reply. I did the same, however I solved the issue just changed the language from VHDL to Verilog in MIG and made new project in ISE Design suite. Copied all the data and then simulation. Its working fine. Thank you :)