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Visitor danhdoanes
Registered: ‎02-08-2017

Need help on QDRII+ implementation

Hi everyone,


I'm Danh and I'm a newbie on FPGA field.

Currently, I'm working for a project and I have to interface QDRII+.

I follow the example design from Xilinx, at this time, the calibration is done when I simulate the example design.

However, when I try to implement this design, I use the example_top.v module, and the calibration is failed.


In this project, I use NetFPGA CML kintex-7 (xc7k325t-1ffg676). It has 2 system_clk p/n (200MHz),

but to use QDRII+, we need sys_clk_p/n run at 450.045 MHz and clk_ref_p/n run at 200MHz, so I use DCM_MMCM to generate these 4 clock from system_clk.

p/n. So I modify a bit in the .ucf file (from example design), that I remove 4 given clocks and write again for 2 system_clk.

I dont know if my approach is correct or not.


Can you give me some hints to get this work done. I'm stuck for 3 months and I dont know what to do now.


Thanks in advance.

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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: Need help on QDRII+ implementation



Clock cascading is not recommended due to jitter effects.


Did you try changing the memory clock period so the GUI input clock period of 200Mhz is shown and you can directly use system clock with out MMCM.


Also check the HW debug section in UG586



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