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theynab2015
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Registered: ‎12-05-2015

Need help with Testbench

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Hey guys.  I am trying to set up a test bench for my call and cncl buttons. (which are my inputs) . Both inputs call and cncl are initially 0.  Call becomes 1 for 2 cycles.  Both inputs are 0 for 2 more cycles, then cncl becomes 1 for 1 cycle.  Both inputs are 0 for 2 more cycles , then both inputs call and cncl become 1 for 2 cycles.  Both inputs become 0 for 1 last cycle.   Here is my code which gave me no errors.

I have an idea of how to set it up but keep getting weird simulation results. Thank you.

 

entity flight6 is
    Port ( call : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           cncl : in  STD_LOGIC;
           res : in  STD_LOGIC;
           light : out  STD_LOGIC);
end flight6;

architecture Behavioral of flight6 is

type state is (lightoff,lighton);
signal current_state, next_state : state :=lightoff;

begin
comb_process: process (current_state, call,cncl)

begin

case current_state is

when lightoff =>

light <= '0';

if call = '0' then

next_state <= lighton;
else next_state <= lightoff;
end if;
when lighton =>
light <= '1';
if not(call and cncl) = '1' then
next_state <= lightoff;
else next_state <= lighton;
end if;
end case;
end process comb_process;

clk_process:process
begin
wait until (clk'event and clk='1');
if (res = '1') then
current_state <= lightoff;
elsif (clk'event and clk='1') then
current_state<=next_state;
end if;
end process clk_process;

 

 

end Behavioral;

 

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arpansur
Moderator
Moderator
7,059 Views
Registered: ‎07-01-2015

Hi @theynab2015,

 

Welcome to Xilinx Forums Community.

 

Coming to your query:

I tried with following testbench for your code.

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_forum IS
END tb_forum;

ARCHITECTURE behavior OF tb_forum IS

COMPONENT flight6
PORT(
call : IN std_logic;
clk : IN std_logic;
cncl : IN std_logic;
res : IN std_logic;
light : OUT std_logic
);
END COMPONENT;

--Inputs
signal call : std_logic := '0';
signal clk : std_logic := '0';
signal cncl : std_logic := '0';
signal res : std_logic := '0';

--Outputs
signal light : std_logic;

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: flight6 PORT MAP (
call => call,
clk => clk,
cncl => cncl,
res => res,
light => light
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res<='1';
wait for clk_period*10;
res<='0';
call<='0';
cncl<='0';
wait for clk_period*10;
call<='1';
wait for clk_period*2;
call<='0';
cncl<='0';
wait for clk_period*2;
--call<='0';
cncl<='1';
wait for clk_period*1;
call<='0';
cncl<='0';
wait for clk_period*2;
call<='1';
cncl<='1';
wait for clk_period*2;
call<='0';
cncl<='0';
wait for clk_period*1;

-- insert stimulus here

wait;
end process;

END;

 

Attaching the snapshot of the testbench. Please verify if the testbench results are the expected results else let us know your requirements.

 

Thanks,
Arpan

 

 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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4 Replies
arpansur
Moderator
Moderator
7,060 Views
Registered: ‎07-01-2015

Hi @theynab2015,

 

Welcome to Xilinx Forums Community.

 

Coming to your query:

I tried with following testbench for your code.

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_forum IS
END tb_forum;

ARCHITECTURE behavior OF tb_forum IS

COMPONENT flight6
PORT(
call : IN std_logic;
clk : IN std_logic;
cncl : IN std_logic;
res : IN std_logic;
light : OUT std_logic
);
END COMPONENT;

--Inputs
signal call : std_logic := '0';
signal clk : std_logic := '0';
signal cncl : std_logic := '0';
signal res : std_logic := '0';

--Outputs
signal light : std_logic;

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: flight6 PORT MAP (
call => call,
clk => clk,
cncl => cncl,
res => res,
light => light
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res<='1';
wait for clk_period*10;
res<='0';
call<='0';
cncl<='0';
wait for clk_period*10;
call<='1';
wait for clk_period*2;
call<='0';
cncl<='0';
wait for clk_period*2;
--call<='0';
cncl<='1';
wait for clk_period*1;
call<='0';
cncl<='0';
wait for clk_period*2;
call<='1';
cncl<='1';
wait for clk_period*2;
call<='0';
cncl<='0';
wait for clk_period*1;

-- insert stimulus here

wait;
end process;

END;

 

Attaching the snapshot of the testbench. Please verify if the testbench results are the expected results else let us know your requirements.

 

Thanks,
Arpan

 

 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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aher
Xilinx Employee
Xilinx Employee
3,675 Views
Registered: ‎07-21-2014
Hi,

Please refer XAPP given in this AR for efficient test bench writing.
http://www.xilinx.com/support/documentation/application_notes/xapp199.pdf

-Shreyas
----------------------------------------------------------------------------------------------
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theynab2015
Visitor
Visitor
3,498 Views
Registered: ‎12-05-2015

Hey sorry for the delay but the testbench is positive. Thank you.  I was wondering how do you  change the name under "value" to make it say light on and light off.  when i try , it doesn't allow me to edit to add names to the other states. btw i am using version 14.1  thank you

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arpansur
Moderator
Moderator
3,485 Views
Registered: ‎07-01-2015

Hi @theynab2015,

 

Please go through the attached snapshot. Please let me know if you need more details on this.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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