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Visitor parthns89
Visitor
2,643 Views
Registered: ‎02-03-2014

ODDR module does not work for clock signal

Hi All,

 

I am seeing a very weird issue while using ODDR module for 7 series FPGA. I have used the same ODDR for data and it works perfectly for data where sampling takes place at next rising edge of clock pulse but it does not work with clcok where new clock pin values are sampled at the same edge.

Code Snippet:  

 

clk_logic : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", --"SAME_EDGE", --DOPPOSITE_EDGE", -- "SAME_EDGE"
INIT => '0',
SRTYPE => "ASYNC")
port map
(D1 => CLK_OUT(0),
D2 => CLK_OUT(1),
C => clk_in,
CE => clock_en,
Q => clk_out,
R => RESET,
S => '0');

 

For data signals, I have used the following instance:

oddr_inst : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", --"SAME_EDGE", --OPPOSITE_EDGE", -- "SAME_EDGE"
INIT => '0',
SRTYPE => "ASYNC")
port map
(D1 => DATA_OUT(pin_value),
D2 => DATA_OUT(s_width + pin_value),
C => clk_in,
CE => clock_en,
Q => data_out(pin_count),
R => RESET,
S => '0');

 

Kiindly help to fix the issue.

Thanks!

Tags (2)
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1 Reply
Xilinx Employee
Xilinx Employee
2,636 Views
Registered: ‎01-03-2008

Re: ODDR module does not work for clock signal

You have active signals connected to D1 and D2, and these should' be 1 and 0.
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