05-24-2016 10:26 PM
Is OpenCL support using the MPSOC ARM as the host planned to be in the roadmap (not x86 as SDAccel).
Meaning running an application on the ARM using linux for example (Vxworks or other RT OS is preferred), and writing OpenCL kernels which could be run on the FPGA core itself (like Altera FPGA/ARM can do).
Our Xilinx representatives here said that currently there is no support but they dont know about the future.
05-25-2016 12:11 PM
05-25-2016 04:54 PM
I think what Eran's asking for is having HLS (or something similar) actually running on the MPSOC itself. Sort of a "reconfiguration from source". Eran, you post seems to indicate that Altera allows this. That's interesting.
The reason why not many (anyone?) would be doing this is a rather long src->bitfile generation process. We're talking minutes at least, if not hours. Most folks for reconfiguration purposes, would have "precomputed" bitfiles, that are already built. At runtime, the desired bitfile would then be loaded.
The MPSOC is supposed to heavily target virtualization. Can't see why you couldn't virtualize a "Xilinx supported" OS running on the device, and then be able to run the whole Xilinx toolset there. That'd be a neat science project, but I don't really see the applicability to anything other than showing you could do it...
05-26-2016 01:27 AM
What I am saying that with altera , I can take an OpenCL code and run it on the arriaV (or other new SOCs) , where the ARM is the host which control the OpenCL framework.
And yes currently the compilation time is very long , but it is almost irrelevant as the first stage is to develop the kernels on a regular PC and only when we are sure it is OK we transform it to the embedded hardware ,
05-26-2016 06:50 AM
Yes, we do that too. Look at SDAccel, and SDSoC packages. OpenCL, and HLS.
The only questions here are whose tools are easier to use, and actually deliver.
I will let you look into that,
05-30-2016 12:09 AM
Hi Austin ,
Thanks for the reply,
But you made me confused again ,
What I am asking for is :
Is that possible ?
Where can I find tutorial which shows some examples for that process (ALTERA support team and documentation helped us with this kind of an example. ).
05-30-2016 03:21 AM
05-30-2016 03:22 AM
>> I think what Eran's asking for is having HLS (or something similar) actually running on the MPSOC itself
apparently that is not the case.
06-01-2016 06:37 AM
I have found a good example of the issue here :
From this example , what I understand is that it is possible to compile (synthesize) OpenCL Kernels as blocks (logic) to be connected to the ARM Block via AXI.
Calling the blocks from the software side is NOT supported by any OpenCL framework. Managing the pointers , indices and logic should be done by software.
Is that true or am I missing something ?
06-01-2016 06:49 AM
Is the keeper of the standards. As you can see, Xilinx is a member. Implementing OpenCL is more an exercise in creating the environment and drivers for any given technology. There is no one single solution. Coding in a way that is agnostic (without any intention of CPU, GPU, or FPGA device) may be the lofty goal, but in reality, if power or performance is the goal, one will be targeting FPGA devices.
If portability is all you care about, then stick to the standard, and ignore implementation (that is a Xilinx problem, not yours).
06-01-2016 07:10 AM
>> From this example , what I understand is that it is possible to compile (synthesize) OpenCL Kernels as blocks (logic) to be connected to the ARM Block via AXI.
>> Calling the blocks from the software side is NOT supported by any OpenCL framework. Managing the pointers , indices and logic should be done by software.
SDSoC helps quite a bit with creating drivers, adding dma to the hardware etc. in area of software support/control of generated IP but I am not sure how much of that support is for OpenCL. I've heard that they do this even for RTL block so it should be possible to get quite a bit out of it even by integrating HLS produced IP.
06-01-2016 09:56 PM
I care for both, performance & portability (One of OpenCL goals) but also for a proper support so I will sum my conclusions for the Xilinx hardware and tools:
Thanks anyway for all of you guys,
06-02-2016 06:53 AM
Which Xilinx field people are you talking to? Please email me (firstname.lastname@example.org) with their contact information. We have training materials for all our tools, so they have no excuses. They also have the customer facing roadmap. If not, we have to go solve that problem, first.
Sounds like you have your points of contact (plural) AND your support. Every question is being answered quickly and accurately (at least here in the forums).
If you wish to see the complete roadmap, that requires a NDA, as we are not going to discuss our future plans in a public forum.