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mugundhaniia
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Registered: ‎09-05-2014

PLL Black box in System Generator

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Hello all,

 

I'm trying out my hand in system generator. So, I was trying to import some PLL modules that I created in xilinx ISE to system generator using Black Box. When I configure my PLL to lower speeds than the Sysgen clock period, then I'm able to view the clock outputs clearly. But when it's made to output higher speed clocks, then the speed of the clock I see in wave scope is 1/2 that of the system clock.

 

Why is this ? Is this got something to do with the simulink system period ?

 

Will this follow during implementation also? or will there be any timing errors because of this ?

 

Thank you,

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bwiec
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Registered: ‎08-02-2011

Hi,

 

I would not recommend that you do this. One of the purposes of sysgen is to abstract things like explicit clock stuff from the user (notice there aren't any clock pins on any of the blocks?). Clocking and I/O stuff in particular are usually better done in a top-level ISE project that ties everything together.

 

ISE sysgen had the 'Multiple Subsystem Generator' for supporting multiple clock domains, so you can use it to handle such scenarios. But I'd put the PLL and any other clock generating logic outside of sysgen and use its output clocks to drive the sysgen clock inputs.

 

I also want to make sure it's clear that the Multiple Subsystem Generator flow is only required for situations where you have truly asynchronous clocks. If you, for example, have a 100MHz clock but only are taking in 1MSPS of synchronous data on a particular input, you don't need to use separate clocks. You can still use the 100MHz clock but a clock enable that only asserts 1 out of 100 clock cycles. Sysgen will automatically do this for you based on sample rate settings.

 

I'd have a read through the 'Timing and Clocking' section of UG640. It might also be helpful to go through the labs in UG639 and/or play with some of the sysgen examples that ship with the tool.

www.xilinx.com

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

Hi,

 

I would not recommend that you do this. One of the purposes of sysgen is to abstract things like explicit clock stuff from the user (notice there aren't any clock pins on any of the blocks?). Clocking and I/O stuff in particular are usually better done in a top-level ISE project that ties everything together.

 

ISE sysgen had the 'Multiple Subsystem Generator' for supporting multiple clock domains, so you can use it to handle such scenarios. But I'd put the PLL and any other clock generating logic outside of sysgen and use its output clocks to drive the sysgen clock inputs.

 

I also want to make sure it's clear that the Multiple Subsystem Generator flow is only required for situations where you have truly asynchronous clocks. If you, for example, have a 100MHz clock but only are taking in 1MSPS of synchronous data on a particular input, you don't need to use separate clocks. You can still use the 100MHz clock but a clock enable that only asserts 1 out of 100 clock cycles. Sysgen will automatically do this for you based on sample rate settings.

 

I'd have a read through the 'Timing and Clocking' section of UG640. It might also be helpful to go through the labs in UG639 and/or play with some of the sysgen examples that ship with the tool.

www.xilinx.com

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mugundhaniia
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Registered: ‎09-05-2014

Hello bwiec ! 

 

Thanks for the reply ! May be that's why I was getting rate assertion errors when I tried to wrap a FIFO generator FIFO in a black box and used this PLL black box to clock it (?)

 

On a different note, I want to use an application where I'd be streaming in data at 4 MHz and taking out data at 100 MHz. The board we're using is CASPER (https://casper.berkeley.edu/) and these guys have a sysgen based development tool suite. I was thinking I'd use the TO fifo and FROM fifo blocks for my application, where I have the input as 8 bits and I must pack this 8 bits to 64 bits. But when I try this in FROM FIFO block, sysgen gives me an error saying a bitwidth mismatch occured b/w i/p and o/p. IS there a work around for this or do we need to revert back to ISE to do this ?

 

Thank you,

 

Mugundhan

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011
Hello,

Yeah it's possible. Sysgen just isn't setup to handle explicit clocking like this so strange things happen.

If your clocks are asynchronous, you can use the multiple clock domain flow with separate clock sources. However, the FIFO block won't automatically pack the data from several 8 bit samples up to 64 bits. You'll have to do it manually so the data matches.
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mugundhaniia
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Thank you for the clarification :D

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mugundhaniia
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Also, at what rate does the FIFO's write happens ? i.e, I have a sysgen block config saying a master clock of 10 ns and system period to be 1, and I set my counter's explicit period to be say, 25, then the counter is counting at 4 MHz and i connect the output of the counter to a FIFO. Now this fifo's write clock will be clocking at 10 ns ? or at 250 ns ? Also, how will these this counter be synthesizable and implementable (is this a valid multirate implementation) or is this only simulatable ?

 

Thank you,

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

Since your system period is 1 and your counter's explicit sample period is 25, that means the clock will increment once every 25 clock ticks. If you connect a 10ns clock, that means the counter will increment every 250ns. Do note that this is done by means of a clock enable, not by a separate clock. It still runs on 10ns clock but a clock enable pulses every 25 clock ticks.

 

The FIFO's write clock will be driven by the domain from which the write data is coming. So in your case, it would be 10ns. You can use the write enable on the FIFO to qualify the data as well (you might find the clock enable probe signal useful... :)).

 

I also find the 'Waveform Viewer' useful for setting up this stuff.

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mugundhaniia
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Registered: ‎09-05-2014

Hello

 ,Everytime when I try to change my sysgen Xilinx " System Generator" token's Multirate implementation parameter to DCM-CE based. See attached screen shot. The error I got was the following: ##################################################################################################### Error using xlSaveBack2Mask (line 17) Invalid setting in Xilinx System Generator Block block (mask) ' System Generator1' for parameter 'clock_wrapper' Error in xlSaveBlockInfo (line 354) Error in xlSysgenGUI (line 121) Error while evaluating uicontrol Callback ##################################################################################################### xilinx_issue.png

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