I am using the DLC9 Platform USB Cable to program a Spartan XL device in Slave Serial Mode with Impact 7.1i and I am running into a weird issue.
Occasionally the CCLK and DIN will start before the /INIT signal on the FPGA is deasserted. This causes a CRC error to occur and the /INIT line to go low again since the data is out of sync. Sometimes the CCLK/DIN begin after /INIT goes high and everything programs correctly.
I have used the cable to program a Spartan II device and it seems to work fine. There is a ~1.4ms delay on the Spartan II for the CCLK/DIN beginning after /INIT goes high though compared to a very small delay on the Spartan XL.
It seems like the Platform Cable does not check to see that /INIT is high before beginning the CCLK/DIN sequence. Is there anyway to delay this data?
I tried decreasing the speed of the CCLK in Impact to 750KHz but that has not helped.