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2,789 Views
Registered: ‎09-07-2016

Post implementation simulation

Hello,

 

I have generated post implementation netlist by using below commands, but I am confused regarding how to map RTL I/Os to netlist I/Os with the same module, so Test bench can drive the I/Os In netlist file, I see there is wrapper around what is supposed to be the top (top in RTL) and again there is one parent which have only two input sysclk and sysrst.

 

1. write_sdf -mode timesim C:/AtomicSub_ip.sdf
2. write_verilog -mode timesim -sdf_anno true -sdf_file C:/AtomicSub_ip.sdf C:/AtomicSub_ip.v

 

Thanks,

Urvish

 

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5 Replies
muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

@urvish_panchal89 if you did things properly, the RTL top level & gate-level top level ports should be identical. 

 

>>  I see there is wrapper around what is supposed to be the top (top in RTL) and again there is one parent which have only two input sysclk and sysrst.

 

I am afraid this sentence is not very clear to me. What exactly is the problem?

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2,768 Views
Registered: ‎09-07-2016

Hi Muzzafer,

 

# I see there is wrapper around what is supposed to be the top (top in RTL) and again there is one parent which have only two input sysclk and sysrst.

I have attached 3 files. If you look at it, you will understand.

AtomicSub_ip_gatelevel.v :- Gate-level file.

AtomicSub_ip_dut_1.v      :- RTL top level module source file

AtomicSub_ip_src_Atomic_Subsystem_2.v  :- RTL source file

 

#if you did things properly, the RTL top level & gate-level top level ports should be identical.

Can you elaborate since ports are not identical.

 

Thanks

Urvish

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arpansur
Moderator
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Registered: ‎07-01-2015

Hi @urvish_panchal89,

 

Can you share a small testcase explaining the issue?

Thanks,
Arpan
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muzaffer
Teacher
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Registered: ‎03-31-2012

@urvish_panchal89 there are no files attached to this thread, so try posting again with attachments.

If you have only clock & rst going into the chip, it means that the implementation has removed all of your logic which means your logic wasn't showing input pin to output pin connectivity. You need to test your design more thoroughly for pin to pin functionality.

 

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2,704 Views
Registered: ‎09-07-2016

Hi Muzzafer, I have attached files now.

 

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