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Registered: ‎08-23-2016

Problem in implementing PCIE targeted reference design

I am trying to implement pcie trd by reffering  ug961-zc706-evaluation-board-gsg pdf for Vivado Design suite version 2015.4.Here, When I try to boot zc706 in SD boot mode, “random: nonblocking pool is initialized” appears (highlighted in figure A) at last zynq prompt message appears ( page no. 22 step 8). When I try to  boot linux  on host pc  (after the QSPI mode booting step (page no. 22 step 10)), “random: nonblocking pool is initialized” message displays on Terminal Program (Tera Term Pro). I also observe that my application is not running properly as no colorbar displays on my HDMI monitor and in QT based application (running on HDMI monitor) also there is no change of Mode appears while I try to change mode in Control and Monitor GUI on the host system.

      Also in Performance Mode when I am starting GUI from the video path panel I observed that in the aggregate PCIe statistics panel Transmit and Receive rates are 32.00 Gbps displayed (highlighted in figure B) which is not maching with the Transmit and Receive rates shown in figure 3-14 of the ug961 document. Kindly provide solution for these queries.

Thanks and Regards

Juhi (IPR)

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Figure A.png
Figure B.jpg
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