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215ee1139
Visitor
Visitor
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Registered: ‎03-04-2017

Problem in understanding of video timing controller IP architecture

Hello

I am reading Video timing controller IP core from the application note pg016_v_tc. I am unable to understand the architecture given in page number 44. I am not understanding how the horizontal and vertical counters are getting inputs as their output is connected to counter save but no input is shown, also what is the working of lock generator here. How this polarity detector is working. Please suggest any documents or videos for understanding working of IP cores as I am having only application notes of respective IP cores only.

Thanks and regards

v_tc.JPG

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florentw
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Registered: ‎11-09-2015

Hi @215ee1139,

 

The horizontal counter and vertical counter are just counting the number of pixels between two hsync/vsync.

 

I don't know how this polarity detector (there is no documentation about that) is working but to do it I would just look a hsync/vsync if the signal is more oftenly high or low.

But you don't have to know really how it works to be able to use the IP.

 

To understand (a bit) more the VTC, I advise you to look at the design from xapp1285 (link) as it use both generator and detector.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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