Problem in understanding of video timing controller IP architecture
I am reading Video timing controller IP core from the application note pg016_v_tc. I am unable to understand the architecture given in page number 44. I am not understanding how the horizontal and vertical counters are getting inputs as their output is connected to counter save but no input is shown, also what is the working of lock generator here. How this polarity detector is working. Please suggest any documents or videos for understanding working of IP cores as I am having only application notes of respective IP cores only.