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Observer
Observer
1,151 Views
Registered: ‎07-29-2014

Problem setting a second reconfiguration module as active

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Hello,

 

I am trying to partially reconfigure four multipliers(8x8,16x16,32x32 and 64x64) using plan ahead. I am following the steps of UG744(Partial reconfiguration of processor tutorial). I have downloaded the four .ngc files into plan ahead and I have  implemented the first reconfiguration (64x64). When i try to set second reconfiguration module (32x32) as high , it shows an error ;

 

 

ERROR: [Netlist 29-77] Could not replace (cell 'rp', library 'rp_lib_mult_pr_0/USER_LOGIC_I/rp_instance_sixtyfour', file 'rp.ngc') with (cell 'rp', library 'rp_lib', file 'rp.ngc') because of a port interface mismatch; 128 ports are missing on the replacing cell. 5 of the missing ports are: 'ain[63]' 'ain[62]' 'ain[61]' 'result[65]' 'result[64]'.
ERROR: [Common 17-53] User Exception: Failed to set active configuration for Partition 'system/mult_pr_0/mult_pr_0/USER_LOGIC_I/rp_instance', Reconfigurable Module 'thirtytwo'. Check that the correct top level file is selected.

 

Any help is appreciated.

 

Thanks in advance

Anup.

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Xilinx Employee
Xilinx Employee
1,587 Views
Registered: ‎09-20-2012

Hi Anup,

 

A reconfigurable partition must contain a super set of all pins to be used by the varying reconfigurable modules implemented for the partition. It is expected that this will lead to unused inputs or outputs for some module variants, and is designed into the flexibility of the PR solution. The unused inputs will be left dangling inside of the module and will cause the implementation tools to issue messages that you may ignore.

 

In the case of a black box RM (no logic) all partition pin outputs will be driven by a constant Logic 1. In the case of a logic RM where there are unused partition pins, these outputs will be tied to constants, but the value may be a Logic 0 or a Logic 1.

 

If your design requires a specific value, these ports should be tied off to the required values in the RM.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
1,588 Views
Registered: ‎09-20-2012

Hi Anup,

 

A reconfigurable partition must contain a super set of all pins to be used by the varying reconfigurable modules implemented for the partition. It is expected that this will lead to unused inputs or outputs for some module variants, and is designed into the flexibility of the PR solution. The unused inputs will be left dangling inside of the module and will cause the implementation tools to issue messages that you may ignore.

 

In the case of a black box RM (no logic) all partition pin outputs will be driven by a constant Logic 1. In the case of a logic RM where there are unused partition pins, these outputs will be tied to constants, but the value may be a Logic 0 or a Logic 1.

 

If your design requires a specific value, these ports should be tied off to the required values in the RM.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos