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prakashdrj
Observer
Observer
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Registered: ‎07-12-2016

RATE change in GTX zynq-706

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How to change RATE in GTX zynq-706, UG467 V1.11.1 described RATE change sequence for GTH Only via [TX/RX]RATE[2:0] signals? Is there any sequence for GTX?

 

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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @prakashdrj

 

Compare the generated _gt.v/.vhd files to find the attribute differences.

 

Thanks,

Vinay

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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @prakashdrj

 

You can achieve this using DRP functionality.

Check this forums thread: https://forums.xilinx.com/t5/7-Series-FPGAs/Questions-about-Kintex-7-GTX-drp-usage/td-p/305633

 

Thanks,

Vinay

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prakashdrj
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Observer
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Registered: ‎07-12-2016

Ya, DRP is there and I can use. but I want to know If I can use [TX/RX]RATE signal like PCIe have.

 

any way DRP is last option!

 

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vuppala
Xilinx Employee
Xilinx Employee
5,220 Views
Registered: ‎04-16-2012

Hi @prakashdrj

 

You can achieve this by changing TXRATE.

Check the page no. 151 in the following user guide: http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Thanks,

Vinay

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prakashdrj
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Observer
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Registered: ‎07-12-2016

Hello @vuppala,

 

So just by changing RATE signal I can? Doesn't It have sequence like GTH?

 

Thanks,

Prakash

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prakashdrj
Observer
Observer
5,198 Views
Registered: ‎07-12-2016

How can I see all attributes generated/set by wizard? In context of GTX?

 

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saradapr
Explorer
Explorer
5,190 Views
Registered: ‎10-14-2015

Hi @prakashdrj,

 

Hope you checked usage of TXRATE/RXRATE ports? 

 

Generate the GT wizard core for the initial line rate Generate the GT wizard core for the modifying line rate. Compare the core files for both and note the attributes which differ.Then modify the required attributes for new rate change.

 

Give necessary resets, after changing these attributes as given in GT user guide.

 

Thanks,

Sarada

 

 

 

 

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prakashdrj
Observer
Observer
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Registered: ‎07-12-2016

Ok! Understood. Is there any way to find out which attributes are differed? Or shall I have to check all files?

 

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vuppala
Xilinx Employee
Xilinx Employee
9,653 Views
Registered: ‎04-16-2012

Hi @prakashdrj

 

Compare the generated _gt.v/.vhd files to find the attribute differences.

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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prakashdrj
Observer
Observer
5,158 Views
Registered: ‎07-12-2016

Hello @vuppala,

 

I have doubt, should I start DRP operation after gtx_[tx/rx]resetdone_out completes or it is independent of gtx block? suppose after Power-On-Reset, I do DRP for [TX/RX]_DATA_WIDTH but actual gtx_[tx/rx]resetdone_out will be asserted long time after DRP completes? Is it affect DRP Operation?

 

In short DRP should be after gtx_[tx/rx]resetdone_out or irrespective of gtx_[tx/rx]resetdone_out?

 

Thanks,

Prakash

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