UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Observer
Posts: 50
Registered: ‎04-13-2017
Accepted Solution

REG: switching speed of cells in FPGA

Hi, we are using Kintex-7 (410tfbg676-2) , 

what will be the minimum cell delay inside FPGA??????

 

 

Thanks 


Accepted Solutions
Highlighted
Teacher
Posts: 5,146
Registered: ‎03-31-2012

Re: REG: switching speed of cells in FPGA

@yatish you can look at this datasheet: https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

on page 35, you can see the CLB delays where the minimum delay shown seems to be 50ps.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post


All Replies
Highlighted
Teacher
Posts: 5,146
Registered: ‎03-31-2012

Re: REG: switching speed of cells in FPGA

@yatish you can look at this datasheet: https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

on page 35, you can see the CLB delays where the minimum delay shown seems to be 50ps.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Observer
Posts: 50
Registered: ‎04-13-2017

Re: REG: switching speed of cells in FPGA

Thank you