UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer sapan533
Observer
3,672 Views
Registered: ‎06-10-2015

Readback Capture Xilinx cycle by cycle

Hi,

 

I have a qeury related to Readback Capture in Xilinx. I want to be able to read the design signal values cycle by cycle using readback capture. So, this means I will have to stop clock every cycle, do the readback, then move ahead by one clock cycle and then again stop clock and repeat the process.

 

Is there any example which shows how we can stop the clock of FPGA after every cycle? What is the procedure to do enable/disable clock at every cycle? 

 

 

And is it possible to read DSP blocks using readback?

Thanks for the  help.

 

Rds

Sapan

Tags (2)
0 Kudos