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Observer bhuvan.m391
Observer
5,972 Views
Registered: ‎03-04-2016

Rectifying error in Xilinx Description Language format file

Hello ,

 I was in the process creating new Configurable Logics Blocks
(CLB) to the Spartan 6 LX9 FPGA at the layout level hardware description language called Xilinx Description language. While doing so those new CLB named NEW_INSTANCE should be driven by nets, for nets I used existing components Programmable Interconnect points (PIP) values to new nets connecting their CLB and those input pins and output pins are configured by seeing in FPGA Editor.

 

net "Mmux_S[2]_t1[3]_wide_mux_11_OUT7_split<0>" ,

  outpin "Mmux_S[2]_t1[3]_wide_mux_11_OUT7_split<0>" B ,

  inpin "t3<0>" D1 ,

  pip BIOI_INNER_X1Y1 IOI_LOGICINB15 -> D1_OLOGIC_SITE_S ,

  pip CLEXM_X4Y2 X_B -> CLEXM_LOGICOUT3 ,

  pip INT_BRAM_X3Y3 NW2E1 -> SW2B0 ,

  pip INT_X2Y2 SW2E0 -> SW2B0 ,

  pip INT_X4Y2 LOGICOUT3 -> NW2B1 ,

  pip IOI_INT_X1Y1 SW2E0 -> LOGICIN_B15 ,

  ;

 

net "NEW_INSTANCE" ,

  outpin "NEW_INSTANCE" AQ,

    inpin "NEW_INSTANCE" A3 ,

  inpin "NEW_INSTANCE" A2 ,

  inpin "NEW_INSTANCE" A1 ,

  inpin "NEW_INSTANCE" AX ,

  inpin "NEW_INSTANCE" CLK ,

  pip BIOI_INNER_X1Y1 IOI_LOGICINB15 -> D1_OLOGIC_SITE_S ,

  pip INT_X4Y2 LOGICOUT3 -> NW2B1 ,

  pip IOI_INT_X1Y1 SW2E0 -> LOGICIN_B15 ,

  ;

By doing so I while converting those designs back to netlist circuit description file I faced several errors

 

Error: PhysDesignRules : 1709- Incomplete connectivity.The pin <SR> of component block <NEW_INSTANCE> is used and partially connected to network <Mmux_S[2]_t1[3]_wide_mux_11_OUT7_split<0>>. All networks must have complete connectivity throughout the comp hierarchy and the connectivity for this pin must be removed or completed

 

Error : PhysDesignRules:764 - Slew rate not set.Since it is used for output and is IOSTANDARD is LVCM0S25 IOB comp <A0> needs a slew rate to be set

 

Error: PhysDesignRules : 1968 - Drive strength not set Since it is used for output and is IOSTANDARD is LVCM0S25 IOB comp <A0>,OUTBUF needs drive strength < or output termination mode > need to be set

these errors are repeated for all the cpmponents and I am clear on adding new components, nets , pip  at XDL level .Please anyone give me the explanations....

  Thank You,

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