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Visitor vegovin
Visitor
3,474 Views
Registered: ‎10-13-2013

Require minimum clock to Q delay for SPARTAN-3AN

Hi,

 

I am using SPARTAN-3AN device. In order to calculate the hold margin I need to have the minimum clock to Q delay. At the monment datsheet only provide maximun clock to Q delay. Please let me know how to consider this Tcq delay(min) for calculating the hold margin.

 

Regards,

Venkatesh

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4 Replies
Instructor
Instructor
3,466 Views
Registered: ‎08-14-2007

Re: Require minimum clock to Q delay for SPARTAN-3AN

When you built your design, the static timing report will show you min and max timing in the "datasheet" section at the end.  Note that you should select a verbose report and enable the data sheet section in the post P&R static timing generation options.

-- Gabor
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Historian
Historian
3,461 Views
Registered: ‎02-25-2008

Re: Require minimum clock to Q delay for SPARTAN-3AN


@vegovin wrote:

Hi,

 

I am using SPARTAN-3AN device. In order to calculate the hold margin I need to have the minimum clock to Q delay. At the monment datsheet only provide maximun clock to Q delay. Please let me know how to consider this Tcq delay(min) for calculating the hold margin.

 

Regards,

Venkatesh


Hold time on input pins? Or hold time inside the FPGA fabric?

----------------------------Yes, I do this for a living.
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Visitor vegovin
Visitor
3,448 Views
Registered: ‎10-13-2013

Re: Require minimum clock to Q delay for SPARTAN-3AN

Hi,

 

You can give me hold margin with respect to input pin. I would be good if you can share the data for the IC fabric also.

 

Thanks and regards,

Venkatesh

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Historian
Historian
3,441 Views
Registered: ‎02-25-2008

Re: Require minimum clock to Q delay for SPARTAN-3AN


@vegovin wrote:

Hi,

 

You can give me hold margin with respect to input pin.


The Spartan 3AN FPGA Family Data Sheet (DS557) details setup and hold time for various combinations of IFD_DELAY_VALUE and specific parts. Did you read that document? 


I would be good if you can share the data for the IC fabric also.


That same document -- WHICH YOU SHOULD HAVE READ -- has those details, too. Pro Tip: in the FPGA fabric, the slices are designed so that the flops have a zero hold time requirement. 

----------------------------Yes, I do this for a living.
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