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Visitor efaz
Registered: ‎02-01-2016

Run-Time Partial Reconfiguration on ZedBoard

Hi everybody,

I'm working with a ZedBoard for the first time and I went through the Software and Hardware video tutorials on the zedboard.org website. My goal is to set up a run-time partial reconfigurable platform using the Zynq 7000. I was thinking to use the ARM processor with some reconfigurable accelerators on its side. Just to start I'd like to create just two accelerators with Vivado HLS, packaging them with AXI interface and swapping them run-time in a single reconfigurable partition.

I'm new to this platform and Xilinx tools too, so I'm asking your help about important points:


-it's easier to use the included ARM dual-core processor or to use a MicroBlaze soft-processor to set-up a partial run-time reconfigurable architecture? Since the Zynq 7000 already includes both an ARM processor and the PCAP interface I was thinking to use them.


-I found lots of guides and documentation by Xilinx and ZedBoard, but what is the workflow you suggest me to start working on this new platform? Can I start creating a static configuration with Vivado working on a block diagram and then add the reconfigurability? Is yes, in which way? Unfortunately the available tutorials don't use the same board or SoC I'm using or sometimes lack some picies of information.


-Do you know any step by step tutorial to start working using run-time reconfiguration with a tipical Xilinx workflow on a ZedBoard (using the Vivado Suite as much as possible)?


Any other help is welcome!


Thanks in advanace,


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4 Replies
Visitor efaz
Registered: ‎02-01-2016

Re: Run-Time Partial Reconfiguration on ZedBoard

I've also another question: can I use Vivado HLS to create an IP starting from a C code and then using this packaged IP to create a partially dinamic reconfigurable block diagram using Vivado? If yes, which is the work-flow?
Thanks in advance

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Visitor efaz
Registered: ‎02-01-2016

Re: Run-Time Partial Reconfiguration on ZedBoard

I followed a tutorial to create an HW accelerator for the PL in order to work together with the ARM PS.
I used the following work-flow:


-->c simulation
-->c synthesis
-->c/rtl co-simulation
-->export ip


-->create block design
-->generate output file
-->generate hdl wrapper
-->generate bitstream
-->export hardware
-->launch sdk


-->create bsp
-->create application


Now I have some questions:


- If I want to use the PCAP interface to partially reconfigure the PL run-time how have I to modify the work-flow?


- Have I to add some specific block in the block design to be able to use the PCAP?


Thanks in advance

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Visitor efaz
Registered: ‎02-01-2016

Re: Run-Time Partial Reconfiguration on ZedBoard

I used the work-flow shown in a tutorial to partial reconfigure an IP block. First I created two IP using Vivado HLS, which are a multiplier and an adder, both wrapped in the same AXI4-Lite interface, and then I created a block design with one of this IP connected to the Zynq.
I implemented the first configuration (with the multiplier) and the second one (with the adder), the design passed all the verifications and I generated the total and partial bitstreams.
Now I have another problem:

-I tried to configure the FPGA using the Hardware Manager, first programming the Static configuration and then programming the partial bitstream with one of the two IPs. In this way both IPs works fine with a simple program I wrote. In this way I'm also sure that both the reconfigurable modules fit well in the reconfigurable partition.

-I tried to configure the FPGA programming it with an initial configuration with Static part + IP_1. The program runs fine. If then I try to program the IP_2 (using the Vivado Hardware Manager) then the program becomes unable to talk with the peripheral.
I also did other tests to try to find the problem proceeding step by step:

1-Program the FPGA with the static only configuration, then loading one IP, then start the software application --> it works
2-After that stop the software application, re-loading the same IP partial bitstream, start the software application --> it works
3-Stop the software application, erase the current IP, load the same IP partial bitstream, start the software application --> it does not work anymore

At the step 3 it does not matter if I load the same IP ore the other one, after the erasing of the reconfigurable partition, even resetting the application, it does not work. If I try to load the other IP without erasing the reconfigurable partition the result does not change, it does not work even if I reset the software application.

I'm struggling to figure out what the problem can be. Any idea?
Thanks in advance!
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Visitor ftcl123
Registered: ‎01-06-2018

Re: Run-Time Partial Reconfiguration on ZedBoard

Do you know this question?

I meet the same question..

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