02-01-2016 09:01 AM
I'm working with a ZedBoard for the first time and I went through the Software and Hardware video tutorials on the zedboard.org website. My goal is to set up a run-time partial reconfigurable platform using the Zynq 7000. I was thinking to use the ARM processor with some reconfigurable accelerators on its side. Just to start I'd like to create just two accelerators with Vivado HLS, packaging them with AXI interface and swapping them run-time in a single reconfigurable partition.
I'm new to this platform and Xilinx tools too, so I'm asking your help about important points:
-it's easier to use the included ARM dual-core processor or to use a MicroBlaze soft-processor to set-up a partial run-time reconfigurable architecture? Since the Zynq 7000 already includes both an ARM processor and the PCAP interface I was thinking to use them.
-I found lots of guides and documentation by Xilinx and ZedBoard, but what is the workflow you suggest me to start working on this new platform? Can I start creating a static configuration with Vivado working on a block diagram and then add the reconfigurability? Is yes, in which way? Unfortunately the available tutorials don't use the same board or SoC I'm using or sometimes lack some picies of information.
-Do you know any step by step tutorial to start working using run-time reconfiguration with a tipical Xilinx workflow on a ZedBoard (using the Vivado Suite as much as possible)?
Any other help is welcome!
Thanks in advanace,
02-03-2016 09:00 AM
I've also another question: can I use Vivado HLS to create an IP starting from a C code and then using this packaged IP to create a partially dinamic reconfigurable block diagram using Vivado? If yes, which is the work-flow?
Thanks in advance
02-04-2016 06:17 AM
I followed a tutorial to create an HW accelerator for the PL in order to work together with the ARM PS.
I used the following work-flow:
->VIVADO DESIGN SUITE
-->create block design
-->generate output file
-->generate hdl wrapper
Now I have some questions:
- If I want to use the PCAP interface to partially reconfigure the PL run-time how have I to modify the work-flow?
- Have I to add some specific block in the block design to be able to use the PCAP?
Thanks in advance
02-11-2016 03:43 AM