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Contributor
Contributor
1,642 Views
Registered: ‎11-03-2016

SOFT_RESET and constraint problem in GTP RX

My FPGA use XC7A200T-1FFG1156 IC which include 16-lane GTP transceiver,

 

My design need 16-lanes GTP receivers, and generated GTP RX IP core by transceiver wizard,

 

My design code have 16 duplicated design instance (design_0 to design_15),

 

My clock structure is : GTP_RX_Lane0 --> RXOUTCLK0--> PLL --> myCLK

 

instance design_0 use RXOUTCLK0 and myCLK

instance design_1 use RXOUTCLK1 and myCLK

instance design_2 use RXOUTCLK2 and myCLK

...

instance design_15 use RXOUTCLK15 and myCLK

 

SOFT_RESET pin in GTP core gen. is connected to FPGA input button,

 

When I keep push that button, I found some rx parallel lane data (with RXOUTCLK) change between Normal and NG,

 

What is the limited for control pin SOFT_RESET? cannot pull LOW (or HIgh) for too long time?

 

--

 

For more, my constraint in clock part like below,

 

I am not sure my set_clock_groups setting is correct or not,

 

create_clock -period 4.629 -name clk_216M [get_ports CLK_216M_IN_P]
create_generated_clock -name clk_108M -source [get_pins CLK_108M_IN_i_reg/C] -divide_by 2 [get_pins CLK_108M_IN_i_reg/Q]
#create_generated_clock -name clk_uart [get_pins uart_clk_gen_0/inst/plle2_adv_inst/CLKOUT0]
create_generated_clock -name clk_uart_rx -source [get_pins uart_top_0/rxclk_i_reg/C] -divide_by 30 [get_pins uart_top_0/rxclk_i_reg/Q]
create_generated_clock -name clk_uart_tx -source [get_pins uart_top_0/txclk_i_reg/C] -divide_by 30 [get_pins uart_top_0/txclk_i_reg/Q]

create_clock -period 9.018 -name mgtrefclk0_113 [get_ports MGTREFCLK0P_113_IN]
create_clock -period 9.018 -name mgtrefclk0_116 [get_ports MGTREFCLK0P_116_IN]
create_clock -period 9.018 -name mgtrefclk0_213 [get_ports MGTREFCLK0P_213_IN]
create_clock -period 9.018 -name mgtrefclk0_216 [get_ports MGTREFCLK0P_216_IN]

 

set_clock_groups -asynchronous \

-group mgtrefclk0_113 \

-group mgtrefclk0_116 \

-group mgtrefclk0_213 \

-group mgtrefclk0_216 \

-group [get_clocks -of_objects [get_pins epi_mac_clk_gen_0/inst/clkout1_buf/O]] \

-group {clk_216M clk_108M} \

-group clk_uart_rx \

-group clk_uart_tx \

-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt0_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt1_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt2_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt3_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt4_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt5_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt6_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_0/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt7_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt0_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt1_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt2_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt3_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt4_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt5_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt6_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]] \
-group [get_clocks -of_objects [get_pins my_design_RX_APHY_exdes_1/my_design_RX_APHY_support_i/my_design_RX_APHY_init_i/inst/my_design_RX_APHY_i/gt7_my_design_RX_APHY_i/gtpe2_i/RXOUTCLK]]

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Moderator
Moderator
1,525 Views
Registered: ‎02-16-2010

Re: SOFT_RESET and constraint problem in GTP RX

In the lanes showing the issue, can you probe RXBUFSTATUS and RXRESETDONE output from GT?
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