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Visitor satya.es44
Visitor
3,268 Views
Registered: ‎07-10-2014

SPI lines IO standard when the bank voltage operating at 1.35V?

Hi,

 

I am interfacing DDR3  which is operating at  1.35VCC  to Virtex 7 banks where the maximum VCCO voltage is 1.8V. When I am interfacing the DDR3 , I am operating the bank VCCO at 1.35V with SSTL as IO standard. The remaining IOs in the same bank are used as SPI lines. For this SPI lines which IO standard to be used because bank operating voltage is 1.35V? Will LVCMOS IO standard supports?

 

Thanks in advance.

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4 Replies
Moderator
Moderator
3,260 Views
Registered: ‎01-15-2008

Re: SPI lines IO standard when the bank voltage operating at 1.35V?

what is the iostandard of the SPI pins? is it 1.8V lvcmos? 

 

check the 7-series io user guide for the IO standard details and supported in a bank for different vcco combinations.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

check the voh, vol, vih and vil in the datasheet for the IOstandard you will use for the spi lines and the fpga and see if they are compatabile if not you might need level translators

http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf

 

--Krishna

 

 

 

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Visitor satya.es44
Visitor
3,238 Views
Registered: ‎07-10-2014

Re: SPI lines IO standard when the bank voltage operating at 1.35V?

Thanks for the reply..

As hardware side if i put level translator problem will be solved but while creating ucf for the fpga which IO standard to be used because LVCMOS will not support 1.35V.?

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Visitor paulatvti
Visitor
3,170 Views
Registered: ‎04-09-2014

Re: SPI lines IO standard when the bank voltage operating at 1.35V?

Any resolution to this problem?  I have the same issue.  I have a DDR3 memory running at 1.35V so most of my IO on this particular bank (bank15 of XC7A200T) are used for the DDR3.  But there are some IOs left over that I would like to use for other functions.  I have a 1.35V to 3.3V translator wanting to see LVCMOS coming out of the FPGA.  But this is not an option in the XDF with Vivado.  I can't use SSTL135 because it cannot accommodate the VIL and VIH required by the voltage translator.

 

Is there a solution?

Thanks for any help on this.

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Guide avrumw
Guide
3,162 Views
Registered: ‎01-23-2009

Re: SPI lines IO standard when the bank voltage operating at 1.35V?

I can't use SSTL135 because it cannot accommodate the VIL and VIH required by the voltage translator.

 

You probably don't have to worry about this. The Voh and Vol of SSTL135 are not "rail to rail" purely because of the termination. SSTL135 is supposed to be terminated to the midrange voltage (0.675V) with a 50ohm resistor. The 50ohm resistor prevents the output from going rail to rail. If you look at DS182 table 24 (and the corresponding diagrams) you will see the measurement scheme (50ohms to 0.675V for SSTL135, whereas the LVCMOS standards are 1Mohm to ground).

 

In reality, the driver of an SSTL output is identical (or nearly identical) to the corresponding LVCMOS output - the difference in Vol/Voh is simply due to the termination scheme.

 

It is, however, odd that there isn't an LVCMOS135...

 

Avrum

 

 

 

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