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Visitor johanalme
Visitor
1,380 Views
Registered: ‎06-16-2017

Selectmap interface HDL simulation model

Hi there,

I have searched the net for a HDL simulation model for the selectmap Interface. I am writing a controlled clock slave selectmap Master, and would like to have a model to verify my design against. I Write VHDL, but a model in Verilog would of course be fine.

 

Does such a thing exist?

 

Kind regards,

Johan Alme

University of Bergen

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1 Reply
Moderator
Moderator
1,369 Views
Registered: ‎01-15-2008

Re: Selectmap interface HDL simulation model

refer to page 119 from the following link

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sim.pdf

 

 

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