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Adventurer
Adventurer
3,098 Views
Registered: ‎04-13-2017

SerDes / GTX rtnsreceivers

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Hi, i'm using OSERDES 3, it has 2 single ended clock (i.e 1 for input and other for high speed output clock) but GTX  clocks are differentials clock. How can i assign my OSERDES clock  to GTX  pins????????

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: SerDes / GTX rtnsreceivers

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@yatish Can you explain to us exactly what you're trying to achieve? What device are you connecting to the FPGA, and what interface does it require?

 

 

The HP I/O pins (using a SerDes) can technically manage 2400Mbps data rate, since they support DDR4-2400 RAM. However, this is managed through a great deal of technical wizardry involving specialized hardware in the FPGA and carefully-written HDL code provided inside the Xilinx memory interface blocks. For a system that you can build reasonably easily, the limits are much lower; 1600Mbps in DDR mode for HP pins all the way down to 125Mbps in SDR mode for HD pins.

 

For very high-speed data transfer there are the GTX transceivers. These are not just general-purpose pins with a fancy name; the transceivers are blocks of dedicated hardware which exist purely to get data into and out of the chip as fast as possible. Each one is permanently wired to a couple of pins (data and clock); you cannot assign normal signals to those pins and you can't assign the GTX signals to normal pins. The pins (both data and clock) only support differential signalling; the hardware needed to do single-ended output is not physically present on those pins and therefore there's no way to enable it.

 

 

 

 

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Guide avrumw
Guide
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Registered: ‎01-23-2009

Re: SerDes / GTX rtnsreceivers

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Your question doesn't really make any sense. There is no relationship between the OSERDES and the GTX.

 

The OSERDES is a serializer in the "conventional" I/O used for synchronous data - data accompanied by a clock (at least normally). It is clocked from two internal fabric clocks to generate outgoing data.

 

The GTX is a high speed gigabit transceiver. It is primarily intended for high speed clock/data recovery serial communication - the clock is not sent separately (really at all), but is recovered from the datastream. The internal clocking of this is completely different. For a GTX you have an external high quality reference clock (generally a high quality external crystal/VCXO/PLL) that the GTX uses to generates the bit-rate clock for transmitting data. The GTX divides this bit clock down internally and provides a clock to the fabric (TXOUTCLK) for the user to use for generating parallel data for the GTX (which it feeds back on TXUSRCLK/TXUSRCLK2).

 

The clocking structures of these two resources have nothing in common - there is no mechanism to have one generate the clock for the other.

 

Avrum

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: SerDes / GTX rtnsreceivers

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I  thought OSDRES supports the clock up to 2.3Gbps hence i have to use GTX pins,

Thank you.

 

 

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Scholar u4223374
Scholar
5,222 Views
Registered: ‎04-26-2015

Re: SerDes / GTX rtnsreceivers

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@yatish Can you explain to us exactly what you're trying to achieve? What device are you connecting to the FPGA, and what interface does it require?

 

 

The HP I/O pins (using a SerDes) can technically manage 2400Mbps data rate, since they support DDR4-2400 RAM. However, this is managed through a great deal of technical wizardry involving specialized hardware in the FPGA and carefully-written HDL code provided inside the Xilinx memory interface blocks. For a system that you can build reasonably easily, the limits are much lower; 1600Mbps in DDR mode for HP pins all the way down to 125Mbps in SDR mode for HD pins.

 

For very high-speed data transfer there are the GTX transceivers. These are not just general-purpose pins with a fancy name; the transceivers are blocks of dedicated hardware which exist purely to get data into and out of the chip as fast as possible. Each one is permanently wired to a couple of pins (data and clock); you cannot assign normal signals to those pins and you can't assign the GTX signals to normal pins. The pins (both data and clock) only support differential signalling; the hardware needed to do single-ended output is not physically present on those pins and therefore there's no way to enable it.

 

 

 

 

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: SerDes / GTX rtnsreceivers

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i have to send the parallel 8 bit data at 150MHz into serial data at 1.25Gbps,so i thought of using serdes for this because it support upto 1.4GHz. so i used IBUFDS to make single ended clock from differential clock, and i have assigned these single ended clock to OSERDES and i have assigned differential clock to GTX pins.since for my application i need the output from GTX only.

 

this was the mistake i have done .

 

now i have understood that i can't assign serdes output signals  for gtx pins.

Thanks for your valuable information.

 

i have one more question for you.

now i have decided to use GTX only as i need 1oGbps line rate, so i'm thinking to bypass 8B/10B and 64B/66B encoder and decoder, how can i bypass them???? if so is there any problem in that????????

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Guide avrumw
Guide
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Registered: ‎01-23-2009

Re: SerDes / GTX rtnsreceivers

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The answer to this depends almost entirely on what the receiver of this data is expecting...

 

As I mentioned in my earlier post, the "conventional I/O" and the GTX are for completely different communication mechanisms.

 

Conventional I/O is (normally) used for synchronous communication, where the data is synchronous to some clock that is also available to the receiver - the clock can be shared by the transmitter and receiver (system synchronous) or forwarded from the transmitter to receiver (source synchronous). In these communication styles, the phase of the clock is used to extract the data from the data signals.

 

The "normal" receiver of a GTX stream is a high speed receiver that does clock/data recovery (CDR). There is (usually) no common clock shared by the receiver and transmitter; instead the clock is recovered from your datastream.

 

So, if your receiver is expecting "conventional" I/O signalling (where there is a clock that provide a phase reference) then you will not be able to get this to work. The output of the GTX has no known phase relationship to any clock, and hence the receiver will have nothing with which to capture the data.

 

If your receiver is expecting CDR input (which is unlikely given what we know already) then you MUST provide a protocol that allows for CDR to operate - this is what 8b/10b, 64b/66b and some other protocols are designed for.

 

Only if your receiver is expecting a completely asynchronous stream of data (one that it is, for example, oversampled or uses some other asynchronous communication mechanism) can you consider sending non-protocol (8b/10b...) data over a GTX transmitter (and expect it to be received on the other side).

 

So, most likely, you have made an error that cannot be corrected without a board spin.

 

Avrum

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: SerDes / GTX rtnsreceivers

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Hi i'm using Kintex ultrasacle xcku040-fbva676-1-i , if i want to use the serdes , which bank pin i have to assign for serdes signals

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