UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie vipasha11
Newbie
3,826 Views
Registered: ‎07-03-2017

Setting FPGA clock rate

I wanted to oversample an LVDS  based 2 Gbps data. In LVDS, the maximum receiver capabilities I could find was 1600 Mbps. Is there a suitable FPGA for my purpose?

(What specification would determine the oversampling capability of the FPGA?)

0 Kudos
9 Replies
Scholar drjohnsmith
Scholar
3,789 Views
Registered: ‎07-09-2009

Re: Setting FPGA clock rate

nope

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Historian
Historian
3,728 Views
Registered: ‎01-23-2009

Re: Setting FPGA clock rate

Certainly with conventional I/O this is impossible (and not even by a little bit).

 

In theory you may be able to use a GTX/GTH/GT... to oversample the signal, but you will have a variety of challenges to meet...

 

First, you have to convert your LVDS signal to a CML signal to be used by the GT*. I don't generally work in this area, but I suspect this is doable (possibly using some resistors).

 

Second, you will have to configure the GT* to work in some kind of "locked" mode - where the CDR stays locked to the reference clock and doesn't attempt to lock to the incoming bitstream. Again I believe this to be possible, but it isn't one of the "normal" modes of the GT* (and hence you are going to have to do a fair amount of research to figure out how to do this).

 

The maximum rates of the GT* vary depending on the device and type of GT, but some of them go quite fast - more than enough to oversample a 2Gbps input....

 

Avrum

Tags (1)
0 Kudos
Newbie vipasha11
Newbie
3,702 Views
Registered: ‎07-03-2017

Re: Setting FPGA clock rate

Thanks! I also wanted to know if I can use the FPGA to source data at 2 Gbps LVDS, or will have to use some intermediate logic converter in the middle?

0 Kudos
Scholar drjohnsmith
Scholar
3,677 Views
Registered: ‎07-09-2009

Re: Setting FPGA clock rate

nope

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Historian
Historian
3,650 Views
Registered: ‎01-23-2009

Re: Setting FPGA clock rate

Again, not with conventional I/O. However the GT* can do speeds far faster than 2gbps. But again, the GT* cells are primarily intended for CDR appplications. I presume this is the other side of the oversampled 2gbps receiver you asked about originally, but you haven't told us what your application is, and whether you are using some kind of encoding like 8b/10b encoding. If not it is going to be very difficult to reliably recover the data...

 

That being said, if your application is FPGA to FPGA, then why not use a proper GT* based communication protocol like Aurora - that can implement a proper point to point interface at rates far faster than 2gbps.

 

Avrum

 

 

Tags (1)
0 Kudos
Newbie vipasha11
Newbie
3,644 Views
Registered: ‎07-03-2017

Re: Setting FPGA clock rate

So, my ultimate aim would be to source a 2 Gbps known signal pattern and then receive it, and check for the Bit error rate.

0 Kudos
Newbie vipasha11
Newbie
3,560 Views
Registered: ‎07-03-2017

Re: Setting FPGA clock rate

Could you elaborate on how to use the GT* transceivers for my purpose?

 

0 Kudos
Scholar drjohnsmith
Scholar
3,553 Views
Registered: ‎07-09-2009

Re: Setting FPGA clock rate

How long do you have to experiment on this ?

 

this is not the usual way of using the GT receiver or transmitter

    so your going to be very much on you own,

 

unlike the IOB serdes, which by comparison are simple, there is no off the shelf design.

 

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Historian
Historian
3,519 Views
Registered: ‎01-23-2009

Re: Setting FPGA clock rate

Could you elaborate on how to use the GT* transceivers for my purpose?

 

Not really. As I mentioned (and @drjohnsmith also said), this is not the normal way to use the GT* cells. While I believe it is possible to accomplish what you want to do, there are no guidelines for it. You will have to carefully read and understand the documentation for the GT* cell in the device(s) you are using, and determine if/how they can be configured to work in this non-standard, non-protocol way.

 

Avrum

Tags (1)
0 Kudos