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Adventurer
Adventurer
4,378 Views
Registered: ‎12-02-2016

Signal generation on Zynq7020

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Hello,

 

I very new to Vivado, I am trying to generate sine wave and later arbitrary wave using Zynq7020 Soc. I have found that DDS is the way to do that, But I am not able to find any documents which use this device. Any help would be appreciated. 

Thank you.

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Adventurer
Adventurer
7,610 Views
Registered: ‎12-02-2016

Re: Signal generation on Zynq7020

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Update.

I was not able to use DDS but. I wrote simple VHDL code and assign lookup table contains sample values which I got from Matlab, and now I am able to simulate any waveform. Thank you for the help. 

View solution in original post

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Scholar austin
Scholar
4,376 Views
Registered: ‎02-27-2008

Re: Signal generation on Zynq7020

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Adventurer
Adventurer
4,325 Views
Registered: ‎12-02-2016

Re: Signal generation on Zynq7020

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Hi,

I have forced the aclk and set aresetn to active low, Still not able to see a signal on an output pin. 

simulation screen.png
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Scholar austin
Scholar
4,315 Views
Registered: ‎02-27-2008

Re: Signal generation on Zynq7020

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resetn implies it is reset while low,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
4,255 Views
Registered: ‎12-02-2016

Re: Signal generation on Zynq7020

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Hello, Still couldn't find the mistake I am making. I have please have a look, test bench, simulation and block design attached.

Thank you

design_1_blockdiagram.png
design_1_simulation.png
Design_1tb.png
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Adventurer
Adventurer
7,611 Views
Registered: ‎12-02-2016

Re: Signal generation on Zynq7020

Jump to solution

Update.

I was not able to use DDS but. I wrote simple VHDL code and assign lookup table contains sample values which I got from Matlab, and now I am able to simulate any waveform. Thank you for the help. 

View solution in original post

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