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Contributor
Contributor
3,768 Views
Registered: ‎05-12-2015

Simulation error vivado HLS IP creating

Hi I have written this simple code to create an IP in HLS for my vivado design

 

 

#include"ap_int.h"


int transform(ap_int<3> input, int * output)
{
	int s ;
	s=input-1;
	*output=s;


return 0;

}

 

in which both input and output are axi stream interface, axis

 

I created this test bench 

int transform( ap_int<3>, int * );
int main(void){
int i;
int y;
int x;
for (i=0; i<100;i++)
transform(x,&y);
return 0;
}

 and run simulation 

and I receive this msg 

@E [SIM-317] C++ compile error.
@E [SIM-321] EXE file generate failed.
@E [SIM-321] EXE file generate failed.
@E [SIM-331] Aborting co-simulation: C simulation failed, compilation errors.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***
command 'ap_source' returned error code
    while executing
"source C:/Users/DELL/workspace/project0/solution1/cosim.tcl"
    invoked from within
"hls::main C:/Users/DELL/workspace/project0/solution1/cosim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"

first where is C/simulation I just found verilog and vhdl, using vivado HLS 2015.1

 

 

second what is not working when I run the simulation

 

thank you

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3 Replies
Scholar xilinxacct
Scholar
241 Views
Registered: ‎10-23-2018

Re: Simulation error vivado HLS IP creating

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Scholar xilinxacct
Scholar
232 Views
Registered: ‎10-23-2018

Re: Simulation error vivado HLS IP creating

@riwa

Running this on a newer version seems to work... I do note that 'x' is never initialized. I don't know if older versions are more suspectible to that.

Hope that helps

If so, please mark as solution accepted to close this issue. Kudos also welcomed.

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Newbie bougti
Newbie
166 Views
Registered: ‎01-27-2019

Re: Simulation error vivado HLS IP creating

The example given in Comm suite: Vivado IP integration: Demo clip adder works both ways: using .xml file as well using the direct external VHDL integration using adding files one by one. In my exported IP from VIVADO HLS for SQRT .xml import works but external IP addition does not work. It give error as attached in the file. Is there a particular pattern of VHDL coding which suits it? My IP cannot recognise the HDL ports too when adding files one by one. Basically top.vhd should call all the dependent components I believe.
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