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sushmahuddar
Visitor
Visitor
3,681 Views
Registered: ‎11-03-2015

Simulation of Zynq Base TRD 2014.4

Hi ,

 

I am trying to simulate  Zynq Base TRD 2014.4 using Vivado 2014.4. When I run behavioral simulation, I get the following error

 

[USF-XSim 62] 'compile' step failed with error(s). Please check the Tcl console output or '' file for more information.

I opened the compile log & found the following errors

 

ERROR: [VRFC 10-91] oserdes2 is not declared [D:/sushma_huddar/TRD_1/pcie_trd/hardware/vivado/runs/z7_pcie_trd_2014.4.srcs/sources_1/ipshared/logicbricks.com/logicvc_v4_1/c764b255/hdl/src/vhdl/ser7to1_s6.vhd:12]
ERROR: [VRFC 10-1504] unit rtl ignored due to previous errors [D:/sushma_huddar/TRD_1/pcie_trd/hardware/vivado/runs/z7_pcie_trd_2014.4.srcs/sources_1/ipshared/logicbricks.com/logicvc_v4_1/c764b255/hdl/src/vhdl/ser7to1_s6.vhd:12]

The file "ser7to1_s6.vhd" is encrypted.

 

How do I get the simulations running???

 

Please help.

 

Thanks in advance

 

Regards

 

 

Sushma Huddar

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2 Replies
pvenugo
Moderator
Moderator
3,538 Views
Registered: ‎07-31-2012

Hi Sushma,

 

Do you still see this error on simulation?

 

Regards

Praveen


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sushmahuddar
Visitor
Visitor
3,510 Views
Registered: ‎11-03-2015

Hi Praveen,

 

I am unable to carry out simulation due these errors

 

Thanks

 

Regards

 

Sushma Huddar

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