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Visitor rozzen
Visitor
8,200 Views
Registered: ‎12-29-2012

Simulation of fifo_generator_v10

Good day for all!!!

We have design of sensor driver on the Artix 7 – 200T. Currently we use at Vivado 2013.2 as design tools set. On board implementation stage we need to build simulation environment.

Our design has some kinds of fifo memories. (build in fifo, ram based ect.)

On start of simulation we have failure warning: "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."

But, for fast correction of RTL we need only behavioral simulation, no more.

(Problems on fifo_generator_v10_0.vhd line 4203)

ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not…

Of course, we have lot of kinds fifo, but way???

Have someone any ideas?

Thank you.

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16 Replies
Xilinx Employee
Xilinx Employee
8,189 Views
Registered: ‎09-20-2012

Re: Simulation of fifo_generator_v10

Hi,

 

In vivado 2013.2 there is an option to generate post synthesis DCP(structural model) for the FIFO core which allows to run behavioural simulation.

1. Right click on IP core and select "Generate output products".

2. Check the option "Generate synthesized checkpoint" and click on "Generate" as shown below.

 

Capture.JPG

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
8,179 Views
Registered: ‎10-04-2011

Re: Simulation of fifo_generator_v10

And to add to what Deepika stated, you are correct that the built-in FIFO (hard FIFO) only has a structural netlist simulation model. FIFOs created using distributed or BRAM componts have a behavioral RTL model. This structural netlist is common in many built-in FGPA components and is a function of the secureIP libraries being in place to protect the IP logic source from discovery. I realize this may have an impact on simulation time as gate level netlists are slower to simulate, but FIFO netlist simulation time has not been found to be excessive. 

 

OK, hope this helps ...

 

-Scott Campbell

Scholar samcossais
Scholar
7,838 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

I needed this information too. As far as I am concerned, I used to compile libraries with the ISE simulation compile wizard (preferably verilog ones as my code is in Verilog even if my simulator supports mixed VHDL / Verilog sim) .

With Vivado (2013.3) I used the command compile_simlib and it works fine except for a few memory models, namely blk_mem_gen_v8_0, dist_mem_gen_v8_0 and fifo_generator_v11_0 that are missing, whereas for instance fifo_generator_v9_3 is in the xilinxcorelib_ver library. And no, the 3 missing models are NOT inside the secureIP library I built with compile_simlib. I am a bit confused.

Whereas I don't like this practice for library models, I can add the model and compile it in my Modelsim project. But which file should I use ? I added the Verilog file (<fifo_core_name>/fifo_generator_v11_0/simulation/fifo_generator_v11_0.v) first but it is the behavioral model, that is I get the error for the built-in mode. All the other files in the <fifo_core_name>/fifo_generator_v11_0/ folder are in encrypted VHDL, and none are in the simulation folder, so that I don't know which is the right one...

Should I use <fifo_core_name>/fifo_generator_v11_0/fifo_generator_v11_0.vhd ?

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Scholar samcossais
Scholar
7,817 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

Ok, I figured out what file you meant to be compiled.

 

First I thought it was

fifo_core_name/fifo_generator_v10_0/fifo_generator_v10_0.vhd (actually v11_0 in my case)

because the problem was about fifo_generator_v10_0 behavioral model not working in simulation for some modes and I thought there was a structural (netlist) version of this model.

 

but you actually meant

fifo_core_name/fifo_core_name_funcsim.v

 

So the basic solution is not to make the fifo_generator_v10 model work but to basically not use it. So for each FIFO coregen IP we are using in an unsupported mode, we must use the netlist (fifo_core_name/fifo_core_name_funcsim.v) instead of the normal simulation file : fifo_core_name/sim/fifo_core_name.v, because the netlist doesn't call the fifo_generator_v10 model.

 

Is my understanding correct ?

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Scholar samcossais
Scholar
7,628 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

By the way, by checking the file , I realized that the behavioral model will only generate an error when the built-in FIFO is in synchronous mode.


      if (C_IMPLEMENTATION_TYPE == 2) begin
         $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
      end else if (C_MEMORY_TYPE == 4) begin
         $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
         $finish;
      end


Is it correct that the behavioral model works for an asynchronous (C_IMPLEMENTATION_TYPE == 2) built-in FIFO or is this "else" a mistake ?

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Xilinx Employee
Xilinx Employee
7,544 Views
Registered: ‎08-01-2008

Re: Simulation of fifo_generator_v10

To run Structural Simulation of the built-in FIFO, you will need to create a structural model.

In the Vivado GUI, Set IP as Top, run synthesis.
After synthesis is complete, you can write out a back annotated simulation model for the IP by running the following commands from the TCL console accessible from the Vivado GUI.
write_verilog -mode funcsim <corename>.v (for Verilog)
write_vhdl -mode funcsim <corename>.vhd (for VHDL)
Add the model as a simulation only source for the flow to simulate the IP.


For the design that has multiple instances of FIFO Generator, you need to run the rename_ref command before running the write commands.
The rename_ref command is a must for uniquify the FIFO instances, otherwise simulation may fail with some other errors.

You can use the below proc for multiple instances of built-in FIFO core in a design:

proc gen_synth_net { ip_file ip_dir part_name } {
create_project -in_memory -part $part_name
set ip_name [file rootname [file tail $ip_file]]
read_ip $ip_file
synth_design -mode out_of_context -top $ip_name
rename_ref -prefix_all ${ip_name}
write_verilog -mode funcsim -force -file $ip_dir/$ip_name/${ip_name}_post_synth.v
close_project
puts "Wrote Verilog simulation for $ip_name"
return 0
}
Thanks and Regards
Balkrishan
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Scholar samcossais
Scholar
7,542 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

Hi

Thank your for your reply.

 

Can you answer my questions if possible ?


First I thought it was

fifo_core_name/fifo_generator_v10_0/fifo_generator_v10_0.vhd (actually v11_0 in my case)

because the problem was about fifo_generator_v10_0 behavioral model not working in simulation for some modes and I thought there was a structural (netlist) version of this model.

 

but you actually meant

fifo_core_name/fifo_core_name_funcsim.v

 

So the basic solution is not to make the fifo_generator_v10 model work but to basically not use it. So for each FIFO coregen IP we are using in an unsupported mode, we must use the netlist (fifo_core_name/fifo_core_name_funcsim.v) instead of the normal simulation file : fifo_core_name/sim/fifo_core_name.v, because the netlist doesn't call the fifo_generator_v10 model.

 

Is my understanding correct ?



Looking at your answer, I assume it is correct.

 

As I said, I actually already have a file called <fifo_core_name>_funcsim.v in my IP folder (which path is <project_folder>/<project_name>.srcs/sources_1/ip/<fifo_core_name>/)

 

It seems it has been created when I first generated the IP with coregen in Vivado GUI with default settings so that I don't need to use the command lines. I get no error when using this file in simulation.

 

The only problem is that I think this structural model is slower (as it is a netlist) and I was wondering if there was no other better solution to simulate built-in FIFOs.

 

Also my last message, isn't it a bug in your code ?

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Xilinx Employee
Xilinx Employee
7,535 Views
Registered: ‎08-01-2008

Re: Simulation of fifo_generator_v10

The built-in FIFO does not support behavioral simulation prior to 2014.1. We are planning to release behavioral simulation support from 2014.1 onwards. This version expected to release in 1st week of April 14.
Thanks and Regards
Balkrishan
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Scholar samcossais
Scholar
7,534 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

Nice. Then I will try with this new version when it's released. I don't know clearly what is the issue, but I am experiencing really slow simulation compared to my previous simulations. I actually think the SRIO netlist model I am using is the main cause, but I was also investigating around FIFOs (I used a lot in my pipelined interfaces).

 

Thank you, sorry if my first messages were unclear. I was (and am still) a bit confused about the new IP structure and simulation libraries.

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Xilinx Employee
Xilinx Employee
5,382 Views
Registered: ‎08-01-2008

Re: Simulation of fifo_generator_v10

Vivado 2014.1 expected to release in next month. You can try at your end and share your experience.
Thanks and Regards
Balkrishan
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Scholar samcossais
Scholar
5,378 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

Sorry for my multiple messages. I forgot one point that I was mentionning the other day about the behavioral model of fifo_generator_v11_0.

 

I am actually using it too when the FIFO is not a built-in one. Hence the following question I made in my previous message :


@samcossais wrote:
[...]
With Vivado (2013.3) I used the command compile_simlib and it works fine except for a few memory models, namely blk_mem_gen_v8_0, dist_mem_gen_v8_0 and fifo_generator_v11_0 that are missing, whereas for instance fifo_generator_v9_3 is in the xilinxcorelib_ver library. And no, the 3 missing models are NOT inside the secureIP library I built with compile_simlib. I am a bit confused.

Whereas I don't like this practice for library models, I can add the model and compile it in my Modelsim project. But which file should I use ? I added the Verilog file (<fifo_core_name>/fifo_generator_v11_0/simulation/

fifo_generator_v11_0.v)


 

 

In 2014.1, will the new behavioral models such as FIFO_GENERATOR_V11_1 be included in the libraries generated with compile_simlib or do I need to compile it manually again as I did this time ?

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Scholar samcossais
Scholar
5,369 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

I found my own answer to this last problem:

In ug900.pdf p.24 :


IMPORTANT: The compile_simlib option compiles only Xilinx primitives and legacy ISE® Design Suite Xilinx cores. Simulation models of Xilinx Vivado IP cores are delivered as an output product when the IP is generated; consequently they are not included in the pre-compiled libraries created using compile_simlib.


 

I don't think it is convenient at all and I prefer when IP cores libraries were together with the primitive libraries but well... at least I know it is intentional.

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Xilinx Employee
Xilinx Employee
5,334 Views
Registered: ‎08-01-2008

Re: Simulation of fifo_generator_v10

Sure it will be fine. You can check the simulation withVivado 2014,1 release. 

Behavioral simulation is not supported for built in FIFO prior to Vivado 2014.1 release.

 

 

Thanks and Regards
Balkrishan
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Scholar samcossais
Scholar
5,330 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

I had a lot of problems compiling these IP core libraries.

I realized that I need to compile them into separate libraries with the exact same name as the library names mentionned when calling the simulation from Vivado. I already have a simulation environment of my own based on Modelsim and TCL scripts, and I wasn't using the Vivado GUI to launch it so I had a very hard time finding what was wrong (as the files are encrypted, I had no details about why I had compile errors).

 

Also, the DSP macro IP displays hundreds of warnings because of undefined signals. I can see signals are undefined on the waveform, no need to display warnings for this (in my humble opinion).

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Scholar samcossais
Scholar
5,327 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

Following the tips in the simulation user guide (ug900) in order to speed up my simulation, I am now using Unifast libraries in addition to Unisims. But concerning FIFO Generator v11.0, I get the following warning :

"Warning : First word fall through is not supported in unifast library".

Do you know if this will be supported in Vivado 2014.1 ?

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Scholar samcossais
Scholar
5,323 Views
Registered: ‎12-07-2009

Re: Simulation of fifo_generator_v10

By the way this is a part of the TCL script I used in Modelsim to compile the Vivado IP core libraries I use :


    echo \n\n---   Compile Xilinx Vivado IP Core Models (not included in Vivado simulation libraries)   ---\n

    echo \n--    fifo_generator_v11_0   --\n
    vlib my_vivado_corelib/fifo_generator_v11_0
    vmap fifo_generator_v11_0 my_vivado_corelib/fifo_generator_v11_0
    vlog -work fifo_generator_v11_0  \

    ../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/hostif_iread_rd_req_p1_fifo/fifo_generator_v11_0/simulation/fifo_generator_v11_0.v

    echo \n--    blk_mem_gen_v8_0   --\n
    vlib my_vivado_corelib/blk_mem_gen_v8_0
    vmap blk_mem_gen_v8_0 my_vivado_corelib/blk_mem_gen_v8_0
    vlog -work blk_mem_gen_v8_0   \

    ../../xilinx_prj_rx0_vvd_2013/xilinx_prj_rx0_vvd_2013.srcs/sources_1/ip/sum_dvip_setting_ram/blk_mem_gen_v8_0/simulation/blk_mem_gen_v8_0.v


 

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