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Registered: ‎06-26-2014

Simulation vs Hardwrae implementation issues

Hi all,


I am tryign to use 10G BASE-r core and optic cable to program a custom board of DACs/ADCs from the zynq(ZC-706).

The 10G-BASE-R trasnmisssion/reception has been tested and works succesfully with the custom board. 


When I try to add additional logic(sequential), which is controlled by a dervied clock from the system clock, the simulation behaves perfectly as expected from the logic,but the final output after synthesis,implementation and running on hardware doesnt .





I am trying to program an AD5791 DAC ( , so I provide a SCLK,SYNC,SDIN exactly as per manual. The simulation ( both behavioral ,and post-impementation timing simulation) works correctly as expected. When tested separately , without the 10G-BASE core, the additional logic for the SPI signals to the DAC works correctly.


When integrated with the 10G BASE  core , Without any critical warning or error in the synthesis and implementation, I observe that the sync signal frequency doubles in the final hardware realization . ie its on for 1 cycle and off for 12 cycles and has a period of 13 cycles, instead of what it was programmed for ( ON for 2 cycles, OFF for 24 cycles).


Is it possible that I can still have timing/routing issues without getting critical warnings?


Even if there are violations/issues, is it possible the signal frequency doubles and time period halves exactly ?


Vivado version used - 2014.4




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