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shraddha27
Newbie
Newbie
1,264 Views
Registered: ‎12-24-2014

Spartan 6 clock source

Hello, 

I want to generate higher clock frequencies. We are using PLL to get higher levels, but the output data bit received is shifted by one place.

When using the internal clock, the bit is received at correct sequence, while using the PLL ( and keeping the multiplier and divider constants as 1 - effectively achieving same clock frequency at the output) the bit is received with a shift in the data.

We are using Spartan 6 for generating higher clock frequency. Is this the problem regarding delay in generation of clock using PLL? If yes then what is the solution for it can you please explain to me.

 

Thank you.

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mcgett
Xilinx Employee
Xilinx Employee
1,249 Views
Registered: ‎01-03-2008

You need to provide more details on what you perceive the problem to be. Shifted one place relative to what metric? Is this a SDR or DDR interface? Is this in simulation or measured on a board?
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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