05-20-2017 08:24 AM
I have a problem with the addressing of my array. I have written a small example that shows the same problem.
There is no error in the synthesis but the simulation is not running. The line with:
res <= c_mat(int+1)(int+1);
is marked with a blue arrow.
Without the addition in the brackets the simulation runs.
Does anyone have an idea why this might be?
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all; entity topmod is Port ( in_a : in unsigned(17 downto 0); clk : in std_logic; res : out unsigned(17 downto 0)); end topmod; architecture Behavioral of topmod is type c_row_type is array (0 to 1) of unsigned(17 downto 0); type c_mat_type is array (0 to 1) of c_row_type; constant c_mat: c_mat_type := ( ("000000000000000001","000000000000000010"), ("000000000000000011","000000000000000100")); signal int : integer range 0 to 17 := 0; --5bit begin int <= to_integer(in_a(17 downto 13)); res <= c_mat(int+1)(int+1); end Behavioral;
05-20-2017 08:40 PM
It looks like your signal "int" has a range larger than the number of elements in each row and column of the array you're using it to index. The array c_mat is only 2 by 2 of 17-bit unsigned vectors. But then you address it using (int + 1) for each of the array indices. I would expect there to be a range error when you run that line in simulation. Don't you get an error message in the console?
05-21-2017 09:19 AM
No there is no error message. The array in my original code is bigger, so the int value makes more sense in this case.