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Visitor cy-li
Visitor
4,722 Views
Registered: ‎01-10-2016

Stuck in Start Cross Boundary Optimization in VIVADO

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Hi All,

 

I have a design using ram.

Synthesis get stuck in processing "Start Cross Boundary Optimization",

no matter Vivado 2015.2 or 2015.4.

 

It can finish synthesis when I don't use ram in design, 

so I make a assumption that Vivado can work correctly.

 

Here is my runme.log.

Can anyone help me?

thanks.


---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 293.996 ; gain = 122.480
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'FourBit_Trie' [C:/Users/lf2net624/Desktop/FourBit_Trie/FourBit_Trie.v:24]
INFO: [Synth 8-638] synthesizing module 'Stage0' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage0.v:11]
INFO: [Synth 8-256] done synthesizing module 'Stage0' (1#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage0.v:11]
INFO: [Synth 8-638] synthesizing module 'Stage1' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage1.v:13]
INFO: [Synth 8-638] synthesizing module 'rom1' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom1.v:1]
Parameter ROM_WIDTH bound to: 12 - type: integer
Parameter ROM_ADDR_BITS bound to: 4 - type: integer
INFO: [Synth 8-3876] $readmem data file 'level01.txt' is read successfully [C:/Users/lf2net624/Desktop/FourBit_Trie/rom1.v:15]
INFO: [Synth 8-256] done synthesizing module 'rom1' (2#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/rom1.v:1]
INFO: [Synth 8-256] done synthesizing module 'Stage1' (3#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage1.v:13]
INFO: [Synth 8-638] synthesizing module 'Stage2' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage2.v:13]
INFO: [Synth 8-638] synthesizing module 'rom2' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom2.v:1]
Parameter ROM_WIDTH bound to: 16 - type: integer
Parameter ROM_ADDR_BITS bound to: 8 - type: integer
INFO: [Synth 8-3876] $readmem data file 'level02.txt' is read successfully [C:/Users/lf2net624/Desktop/FourBit_Trie/rom2.v:15]
INFO: [Synth 8-256] done synthesizing module 'rom2' (4#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/rom2.v:1]
INFO: [Synth 8-256] done synthesizing module 'Stage2' (5#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage2.v:13]
INFO: [Synth 8-638] synthesizing module 'Stage3' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage3.v:13]
INFO: [Synth 8-638] synthesizing module 'rom3' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom3.v:1]
Parameter ROM_WIDTH bound to: 19 - type: integer
Parameter ROM_ADDR_BITS bound to: 12 - type: integer
INFO: [Synth 8-3876] $readmem data file 'level03.txt' is read successfully [C:/Users/lf2net624/Desktop/FourBit_Trie/rom3.v:15]
INFO: [Synth 8-256] done synthesizing module 'rom3' (6#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/rom3.v:1]
INFO: [Synth 8-256] done synthesizing module 'Stage3' (7#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage3.v:13]
INFO: [Synth 8-638] synthesizing module 'Stage4' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage4.v:13]
INFO: [Synth 8-638] synthesizing module 'rom4' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom4.v:1]
Parameter ROM_WIDTH bound to: 21 - type: integer
Parameter ROM_ADDR_BITS bound to: 15 - type: integer
INFO: [Synth 8-3876] $readmem data file 'level04.txt' is read successfully [C:/Users/lf2net624/Desktop/FourBit_Trie/rom4.v:15]
INFO: [Synth 8-256] done synthesizing module 'rom4' (8#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/rom4.v:1]
INFO: [Synth 8-256] done synthesizing module 'Stage4' (9#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage4.v:13]
INFO: [Synth 8-638] synthesizing module 'Stage5' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage5.v:13]
INFO: [Synth 8-638] synthesizing module 'rom5' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom5.v:1]
Parameter ROM_WIDTH bound to: 22 - type: integer
Parameter ROM_ADDR_BITS bound to: 17 - type: integer
INFO: [Synth 8-3876] $readmem data file 'level05.txt' is read successfully [C:/Users/lf2net624/Desktop/FourBit_Trie/rom5.v:15]
INFO: [Synth 8-256] done synthesizing module 'rom5' (10#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/rom5.v:1]
INFO: [Synth 8-256] done synthesizing module 'Stage5' (11#1) [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage5.v:13]
INFO: [Synth 8-638] synthesizing module 'Stage6' [C:/Users/lf2net624/Desktop/FourBit_Trie/Stage6.v:13]
INFO: [Synth 8-638] synthesizing module 'rom6' [C:/Users/lf2net624/Desktop/FourBit_Trie/rom6.v:1]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 733.387 ; gain = 561.871
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 733.387 ; gain = 561.871
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7v2000tfhg1761-2
INFO: [Device 21-403] Loading part xc7v2000tfhg1761-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 733.387 ; gain = 561.871
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "rom_1" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:52 ; elapsed = 00:01:40 . Memory (MB): peak = 1919.875 ; gain = 1748.359
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 7
23 Bit Registers := 1
22 Bit Registers := 1
21 Bit Registers := 1
19 Bit Registers := 1
18 Bit Registers := 1
16 Bit Registers := 1
12 Bit Registers := 1
8 Bit Registers := 9
1 Bit Registers := 7
+---ROMs :
ROMs := 7
+---Muxes :
17 Input 12 Bit Muxes := 1
2 Input 8 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module Stage0
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
Module rom1
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
+---Muxes :
17 Input 12 Bit Muxes := 1
Module Stage1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
Module rom2
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
+---ROMs :
ROMs := 1
Module Stage2
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
Module rom3
Detailed RTL Component Info :
+---Registers :
19 Bit Registers := 1
+---ROMs :
ROMs := 1
Module Stage3
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
Module rom4
Detailed RTL Component Info :
+---Registers :
21 Bit Registers := 1
+---ROMs :
ROMs := 1
Module Stage4
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
Module rom5
Detailed RTL Component Info :
+---Registers :
22 Bit Registers := 1
+---ROMs :
ROMs := 1
Module Stage5
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
Module rom6
Detailed RTL Component Info :
+---Registers :
23 Bit Registers := 1
+---ROMs :
ROMs := 1
Module Stage6
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 2160 (col length:60)
BRAMs: 2584 (col length: RAMB18 240 RAMB36 120)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Start Parallel Synthesis Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:41 . Memory (MB): peak = 1919.875 ; gain = 1748.359
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------

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1 Solution

Accepted Solutions
Moderator
Moderator
8,609 Views
Registered: ‎01-16-2013

Re: Stuck in Start Cross Boundary Optimization in VIVADO

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@cy-li,

 

• The logic implemented in block RAM must satisfy the following criteria:
– All outputs are registered.
– The block contains only one level of Registers, which are Output Registers.
– All Output Registers have the same control signals.
– The Output Registers have a synchronous reset signal.
– The block does not contain multi-source situations or tristate buffers.
– Keep is not allowed on intermediate signals.
• Vivado attempts to map the designated logic onto block RAM during Low Level
Synthesis. When successful, Vivado issues a message.
Entity <logic_bram_1> mapped on BRAM.
• If any of the listed requirements is not satisfied, Vivado does not map the designated logic onto block RAM, and issues a warning.
INFO: [Synth 8-5544] ROM "rom_1" won't be mapped to Block RAM because address size (4) smaller than threshold (5)

 

Please check this w.r.t to your code and do the necessary modifications.

Also Check page number 100 in below Synthesis User guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

Regards,

Syed

---------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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5 Replies
Moderator
Moderator
8,610 Views
Registered: ‎01-16-2013

Re: Stuck in Start Cross Boundary Optimization in VIVADO

Jump to solution

@cy-li,

 

• The logic implemented in block RAM must satisfy the following criteria:
– All outputs are registered.
– The block contains only one level of Registers, which are Output Registers.
– All Output Registers have the same control signals.
– The Output Registers have a synchronous reset signal.
– The block does not contain multi-source situations or tristate buffers.
– Keep is not allowed on intermediate signals.
• Vivado attempts to map the designated logic onto block RAM during Low Level
Synthesis. When successful, Vivado issues a message.
Entity <logic_bram_1> mapped on BRAM.
• If any of the listed requirements is not satisfied, Vivado does not map the designated logic onto block RAM, and issues a warning.
INFO: [Synth 8-5544] ROM "rom_1" won't be mapped to Block RAM because address size (4) smaller than threshold (5)

 

Please check this w.r.t to your code and do the necessary modifications.

Also Check page number 100 in below Synthesis User guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

Regards,

Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
4,631 Views
Registered: ‎10-24-2013

Re: Stuck in Start Cross Boundary Optimization in VIVADO

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Hi @cy-li

In synthesis settings change the "flatten hierarchy" to NONE and see if that helps.

Thanks,Vijay
--------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
4,516 Views
Registered: ‎10-24-2013

Re: Stuck in Start Cross Boundary Optimization in VIVADO

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Hi @cy-li

Did you try the given options? Post the updates for futher help.

Thanks,Vijay
--------------------------------------------------------------------------------------------
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Visitor cy-li
Visitor
4,494 Views
Registered: ‎01-10-2016

Re: Stuck in Start Cross Boundary Optimization in VIVADO

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Thank for your reply.

 

I have modified the block ram file to satisfy criteria that  @syedz provided.

I realize that it takes 16 hours to finish synthesis.

Thanks to@vijayak , your advice should also be helpful.

 

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Moderator
Moderator
4,429 Views
Registered: ‎01-16-2013

Re: Stuck in Start Cross Boundary Optimization in VIVADO

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@cy-li,

 

Please close this thread by marking the post as "Accept as solution"  so that it will help for other users who could face the similar issue.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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